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Does a cache-writeback flush all outstanding writes to DDR3?

Clemens Eisserer
Expert 2430 points

Hi,

The C6678 mentions:


A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if
master A passes a software message via a buffer in external memory and does not wait for an indication that the write
completes, before signaling to master B that the message is ready, when master B attempts to read the software
message, then the master B read may bypass the master A write and, thus, master B may read stale data and,
therefore, receive an incorrect message.

Does this paragraph mean, its not enough to call a cache-writeback API to make sure data is written in DDR3 when using multiple cores?
Does MFENCE have any influence on uncached DDR3 writes?

Thank you in advance, Clemens

  • 0
    TI__Expert 7180 points

    Hi Clemens,

    From C66x specification standpoint, cache-writeback itself does not imply MFENCE operation.  However, it seems a current implementation of SYS/BIOS for C66 (e.g. v6.33.06.50) is issuing MFENCE (or _mfence() intrinsics function) when waiting for cache operation completion (e.g. Cache_wait()).

    On the other hand, my understanding is, MFENCE itself does not involve cache-write back.  To ensure that data reaches DDR3 endpoint, we need cache write-back and also MFENCE.  Once again, the current cache operation by SYS/BIOS seems issuing MFENCE when applying API function argument (or option) 'wait' as True.

    Please also refer the section 3.8.12.1 "MFENCE Restrictions" of the SPRUGH7 (http://www.ti.com/lit/ug/sprugh7/sprugh7.pdf).

    Best Regards,
    Atsushi

  • 0 in reply to Yokoyama, Atsushi
    Expert 2430 points

    Hi Atsushi,

    Thanks for the confirmation regarding cache-writeback and MFENCE.

    What I am still not sure about is wether I need special procedure when writing to DDR3, beside cache-flush and mfence, as mentioned in the c6678-data manual.
    E.g. when writing to an uncached DDR3 region, when do I need to apply the work-around mentioned in the manual, or is a MFENCE enough to ensure data has been stored in DDR3?

    Thanks again, Clemens

  • 0 in reply to Clemens Eisserer
    TI__Expert 7180 points

    Clemens,

    If the region is cache-disabled by MAR registers, only MFENCE instruction is required to ensure the data is actually stored in DDR3 endpoint.  When the MFENCE instruction completed, other cores and peripherals can safely access the region and read the data.

    Regards,
    Atsushi