Hi all,
I want to enhance core domain clock frequencies, thus DSP frequencies by PLL1's multipier.
I have read 'TMS320DM643x DMP DSP Subsystem reference manual', find out if primary reference clock is 27MHZ, the multiplier range is 15 ~ 22 and frequency range of DSP is 405.0 ~ 594MHZ.
But from data manual from DM6437, as describable below:
The max frequency can be reached at 700MHZ under 30MHZ's primary refencen clock.
My question is:
1) Can we reach 700MHZ, when input clock is 27MHZ?
2) Is have dangerous to exceeds the devices can reach's MAX frequency, for example to exceed 594MHZ, under 27MHZ input clock? if to do this what will be happen?
3) what's mean -7 devices/Q6 devices etc of Upper table? Our DM6437's part number is TMS320DM6437ZWT , not number follow it, Is mean it command for ZWT7/6/5/4/L?
Best Regards
TanYu