Hi,
I need a clarification for VPIF port interface of capture and display port to FPGA.
I plan to interface VPIF port as a HD format standard to FPGA. so i can utilize the all 16 bits of data from capture and display port.
In my design have two FPGA's, so i have configured as,
Capture data (16 bit) interfaced parallel to both FPGA's and Display data (16 bit) interfaced to only one FPGA.
Shall i interface the capture data (16 bit) to both the FPGA's in parallel mode?
What are the constraints needs to follow while designing schematic and PCB?
Regards,
Sivakumar