LCD issues on OMAP4430

Johny,

Checkout the pixel clock rate that is supplied to your panel. Try to reduce the clock rate (in turn the frame rate) and see any difference occurs or not.

Renjith Thomas,

     Thanks you reply .According to you said I reduce the pixel clock rate and the frame rate is 59hz .But it still occur the error but it occur "Unfortunately System UI has stoped "

    
.clocks = {
        .dispc = {
             .channel = {
                .lck_div        = 1,
                .pck_div        = 2,  //PCLK=66.3 Mhz
                .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
            },
            .dispc_fclk_src = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
        },

        .dsi = {
            .regn           = 38,
            .regm           = 394,
            .regm_dispc     = 6,
            .regm_dsi       = 9,
            .lp_clk_div     = 5,
            .offset_ddr_clk = 0,
            .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
        },
    },

My panel timing table :

thanks !

Is there any frame buffer rotation enabled?

No ,these is no rotation enable !when I set LCD resolution 1366*768 it occor these error .But it can display  ok when i use lcd of resolution 1024*768 .I use WB DMA to GFX ,it doesnot occor these error .it occor UI stop.

Did you probe the VSYNC line and check the actual refresh rate? Also did you check the pixel clock frequency that is generated? Also have you tried increasing the pclk_div variable to 3?

When i seted pclk_div variable to 3 ,it cat't display .and i check the pixel clock frequency is66.3Mhz

shell@android:/ # cat d/omapdss/clk                                            
- DSS -
dpll4_ck 1536000000
DSS_FCK (DSS_FCLK) = 1536000000 / 9  = 170666666
- DISPC -
dispc fclk source = DSS_FCK (DSS_FCLK)
fck             170666666       
- DISPC-CORE-CLK -
lck             170666666       lck div 1
- LCD1 -
lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
lck             132715748       lck div 1
pck             66357874        pck div 2
- LCD2 -
lcd2_clk source = DSS_FCK (DSS_FCLK)
lck             42666666        lck div 4
pck             42666666        pck div 1
- DSI1 PLL -
dsi pll source = dss_sys_clk
Fint            1010526         regn 38
CLKIN4DDR       796294488       regm 394
DSS_FCK (DSS_FCLK)      132715748       regm_dispc 6    (off)
DSI_PLL_HSDIV_DSI (PLL1_CLK2)   88477165        regm_dsi 9      (on)
- DSI1 -
dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
DSI_FCLK        88477165
DDR_CLK         199073622
TxByteClkHS     49768405
LP_CLK          8847716

shell@android:/ #cat sys/class/graphics/fb0/modes

U:1366x768-58

Are you able to see something on the display when the value is 3? Please try the value 4 also. 

Please probe the VSYNC/PCLK line to find out the exact frame rate in case of 2,3 and 4. 

The settings are from a software perspective, but it may not 100% translate to the expected frequencies. So we've to calculate based on the actual register values written. That will take time, instead you can just check the clock using an oscilloscope if you have.

i set  the value is 2 and using an oscilloscope to check the pclk is 66.3Mhz

Johny,

How about VSYNC frequency?

The VSYNC = 66357874 / (768+8+8+1) /(1366+24+48+10)=58.2

#define TC358765_WIDTH  1366

#define TC358765_HEIGHT  24

#define TC358765_PCLK 48

#define TC358765_HFP 10

#define TC358765_VFP 1

#define TC358765_VSW 8

#defineTC368765_VBP 8

Johny,

I meant what is the VSYNC frequency that you are seeing on the physical line? I mean when you check using an oscilloscope, are you able to see exactly 58.2Hz?

Johny,

Also one more thing. Can you check the value of the register field DISPC_GFX_ATTRIBUTES->GFXBURSTSIZE? If the value is 0 try 2 and if it is 2 try with 0.

Hi Johnny

Please check that you have the linebuffer disabled on drivers/video/omap2/dss/dsi.c:

should be

That is the register DSI_CTRL[12:13]. This is because this screen is larger than the size of the linebuffer 1280x24bits.

See how that goes and if you still have problems, then please try with the following settings.

I am assuming you are using 4 data lanes.

DSI Blankings are calculated on (on drivers/video/omap2/dss/dsi.c).

Check that the calculated values are:

Vertical DSI blankings are the same as DISPC.

Change if needed.

Let me know how do you do.

Regards

Rafael

Hi Rafae

    Sorry ,Belated Reply. According to what you said, i set register DSI_CTRL[12:13] to zero ,but it can't improve ,it stil occor "UI Stop ". So i try setting  timing that you said .but  this set lead to LCD can't dispaly .

hfp = 22
hbp = 68
hsw = 4
vbp = 13
vfp = 2
vsw = 6

And  i set :

#define TC358765_WIDTH  1366

#define TC358765_HEIGHT  768

#define TC358765_PCLK 69300

#define TC358765_HFP 22

#define TC358765_HSW 68

#define TC358765_HBP 4

#define TC358765_VFP 13

#define TC358765_VSW 2

#defineTC368765_VBP 6

    .clocks = {
        .dispc = {
             .channel = {
                .lck_div        = 1,
                .pck_div        = 2,
                .lcd_clk_src    = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,
            },
            .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
        },

        .dsi = {
            .regn           =16, //38,
            .regm           = 173,//394,
            .regm_dispc     =6, //6,
            .regm_dsi       =5, //9,
            .lp_clk_div     = 5,
            .offset_ddr_clk = 0,
            .dsi_fclk_src   = OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,
        },

shell@android:/ # cat /d/omapdss/clk                                           
- DSS -
dpll4_ck 1536000000
DSS_FCK (DSS_FCLK) = 1536000000 / 9  = 170666666
- DISPC -
dispc fclk source = DSS_FCK (DSS_FCLK)
fck             170666666       
- DISPC-CORE-CLK -
lck             170666666       lck div 1
- LCD1 -
lcd1_clk source = DSI_PLL_HSDIV_DISPC (PLL1_CLK1)
lck             138400000       lck div 1
pck             69200000        pck div 2
- LCD2 -
lcd2_clk source = DSS_FCK (DSS_FCLK)
lck             42666666        lck div 4
pck             42666666        pck div 1
- DSI1 PLL -
dsi pll source = dss_sys_clk
Fint            2400000         regn 16
CLKIN4DDR       830400000       regm 173
DSS_FCK (DSS_FCLK)      138400000       regm_dispc 6    (off)
DSI_PLL_HSDIV_DSI (PLL1_CLK2)   166080000       regm_dsi 5      (on)
- DSI1 -
dsi fclk source = DSI_PLL_HSDIV_DSI (PLL1_CLK2)
DSI_FCLK        166080000
DDR_CLK         207600000
TxByteClkHS     51900000
LP_CLK          16608000
shell@android:/ #
shell@android:/ #
shell@android:/ # cat sys
sys/    system/
vices/platform/omapdss/display0/timings                                       <
69300,1366/22/4/68,768/13/6/2
shell@android:/ #

    lanes = dsi_get_num_data_lanes_dssdev(dssdev);

    hbp = dispc_to_dsi_clock((timings->hsw - 1) + (timings->hbp - 1),
                bytes_per_pixel, lanes);
    printk("#################hbp_dsi=%d\n",hbp);
    hfp = dispc_to_dsi_clock(timings->hfp - 1, bytes_per_pixel, lanes);
    printk("#################hfp_dsi=%d\n",hfp);
    hsa = 0;

    line = timings->hbp + timings->hfp + timings->hsw + timings->x_res;
    printk("#################line_dsi=%d\n",line);
    WARN((line * bytes_per_pixel) % lanes != 0, "TL should be an exact "
            "integer, try changing DISPC horizontal blanking parameters");

    tl =  dispc_to_dsi_clock(line, bytes_per_pixel, lanes);

[    8.257446] omap-rproc omap-rproc.1: remote processor ipu is now up
[    8.270843] omap_rpmsg_mbox_callback: received echo reply from ipu !
[    8.270874] omap_rpmsg_mbox_callback: received echo reply from ipu !
[    8.270874] omap_rpmsg_mbox_callback: received echo reply from ipu !
[    8.270904] omap_rpmsg_mbox_callback: received echo reply from ipu !
[    8.271240] virtio_rpmsg_bus virtio2: creating channel rpmsg-client-sample addr 0x32
[    8.271759] virtio_rpmsg_bus virtio2: creating channel rpmsg-client-sample addr 0x33
[    8.272155] virtio_rpmsg_bus virtio2: creating channel rpmsg-omx addr 0x3c
[    8.272949] rpmsg_omx rpmsg-omx0: new OMX connection srv channel: 1024 -> 60!
[    8.330444] #################hbp_dsi=52
[    8.330444] #################hfp_dsi=15
[    8.330474] #################line_dsi=1460
[    8.459930] omapdss DSI error: rx fifo not empty when sending BTA, dumping data:
[    8.459960] omapdss DSI error:       rawval 0x17000202
[    8.459991] omapdss DSI error:       ACK with ERROR (0x2):
[    8.460021] omapdss DSI error:               SoT Sync Error
[    8.477355] tc358765 display0: reg read 13c, val=00000004
[    8.481414] tc358765 display0: reg read 13c, val=00000004
[    8.513305] tc358765 display0: power_on done
[    8.553619] virtio_rpmsg_bus virtio3: creating channel rpmsg-omx addr 0x3c
[    8.554077] rpmsg_omx rpmsg-omx1: new OMX connection srv channel: 1024 -> 60!
[    8.575805] tc358765 display0: disable
[    8.638427] tc358765 display0: enable
[    8.638427] tc358765 display0: power_on
[    8.751922] #################hbp_dsi=52
[    8.751953] #################hfp_dsi=15
[    8.751953] #################line_dsi=1460

i have a question ,value of hfp hbp out of range ,can LCD display ?

Regards

Johnny

Hi Johnny,

My omap4460 outputs 1920x1200 LCD and has the same problem as yours.

You can use DISPC_GLOBAL_BUFFER to reallocate buffer.

My source code here: https://gist.github.com/4116881

Please refer to dispc.c.diff and dispc.h.diff.

Hi Ping-Chu Hung ,

      I try the suggestion  that you said ,but it would appear "UI Stop" dialog box  on L27.IS.2.M1 Release. When i modified the code (DISPC_GLOBAL_BUFFER) to reallocate buffer on 4AI.1.7P1 Release ,these is OK .I don't konow  why  ? another issues ,when outputs 1920x1200 resolution on another  LCD ,can HDMI display ? HDMI can't display normal on we custom board ,it display half 

Hi Johnny,

Here is the TRM describes pipeline buffer.
http://makelinux.net/lib/ti/OMAP4460/doc-2526

And the meaning of DISPC_GLOBAL_BUFFER is here.
http://makelinux.net/lib/ti/OMAP4460/doc-2746

The default value is 0x246D2240, new value is 0x006D2240.
So the buffers for WB are allocated to GFX.

About the problem of displaying half, I have no idea.

I suggest you trace a lot of codes in drivers/video/omap2/dsscomp and read Display Subsystem in TRM.