Three mmc's on 8148

Alexander Vasiljev

Hi.

The configuration on our 8148 board is mmc0 - wlan, mmc1 - sd-card, mmc2 - sd card. We start working with wlan recently and it still doesn't work. Before it we didn't even configure board to use 3 mmc. We used only mmc1 and mmc2 and they worked well. But now mmc2 permanently fails with all 3 mmc's configured. That is mmc2 is working well, when mmc0 is not configured. Here's the log when all mmcs is configured and a sd-card is inserted in mmc2 slot.

Powering off wl12xx
Powering on wl12xx
mmc0: card claims to support voltages below the defined range. These will be ignore.
mmc0: queuing unknown CIS tuple 0x91 (3 bytes)
mmc0: new SDIO card at address 0001
Powering off wl12xx
mmc1 cd: pstate = 1fa0000
mmc2 cd: pstate = 1fb0000
mmc2: mmc_rescan: trying to init card at 400000 Hz
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 805 [#1]
last sysfs file:
Modules linked in:
CPU: 0    Tainted: G        W    (2.6.37+ #378)
PC is at __bug+0x18/0x24
LR is at __bug+0x14/0x24
pc : [<c003d218>]    lr : [<c003d214>]    psr: 60000013
sp : e724bdb8 ip : 00011ed0 fp : 00000000
r10: e724c000 r9 : e724dc00 r8 : e724bea4
r7 : e724be78 r6 : e724be48 r5 : 00000002 r4 : e724c240
r3 : 00000000 r2 : e724bdac r1 : c046117a r0 : 00000037
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c5387d Table: 80004019 DAC: 00000017
Process kworker/u:1 (pid: 45, stack limit = 0xe724a2e8)
Stack: (0xe724bdb8 to 0xe724c000)
bda0:                                                       e724c240 c02a1314
bdc0: fb810100 00000000 e724be78 e724c000 e724c240 e724be78 00000000 c02a1880
bde0: e724bdec e724dd60 00000000 00000004 c04a52cb 00000001 00000008 e724bea4
be00: e724c000 e724bea4 e724dd60 c0296114 00000200 00000064 00000000 00000000
be20: 00000000 00000001 e724be28 e724be28 e724be78 e724be78 00000008 e724be48
be40: e724beb8 c02997f8 00000033 00000000 00000000 00000000 00000000 00000000
be60: 000000b5 00000000 00000000 00000000 e724be78 e724bea4 05f5e100 00000000
be80: 00000008 00000001 00000000 00000200 00000000 00000000 e724bea4 00000001
bea0: e724beb8 e724be48 e724be78 00000000 e724be24 c029665c c0a5f9a2 00000d60
bec0: 00000008 a724dd60 e724c000 e724dc00 00000000 e724dc00 e724bf18 00000000
bee0: 00000000 e724c000 00000000 c02986fc e724c000 e724dc00 e724dc00 00000000
bf00: e724c000 e724bf18 00000000 c0295a74 e724c1c8 c0298f2c 02544d53 44303247
bf20: 60a7736b a100a8a7 e724c000 ffffff92 e724bf5c 00000000 c03c8e28 c02990e0
bf40: e724c000 00ff8000 00000001 e724c000 ffffff92 c0295cf8 e724c1c8 00ff8000
bf60: 60000013 e724c1c8 c05657b8 e722c940 c0565768 e70bca00 00000000 c006ccb8
bf80: e722c940 e722c940 c0565768 00000089 c0565768 c0565768 e722c950 e724a000
bfa0: 00000000 c006d5c0 e724bfd4 e7039f28 e722c940 c006d414 00000000 00000000
bfc0: 00000000 c007132c c003aaf8 00000000 e722c940 00000000 e724bfd8 e724bfd8
bfe0: 00000000 e7039f28 c00712a8 c003aaf8 00000013 c003aaf8 fd9ffffa fd71f5f7
[<c003d218>] (__bug+0x18/0x24) from [<c02a1314>] (omap_hsmmc_start_command+0x168/0x1ec)
[<c02a1314>] (omap_hsmmc_start_command+0x168/0x1ec) from [<c02a1880>] (omap_hsmmc_request+0x3bc/0x3f4)
[<c02a1880>] (omap_hsmmc_request+0x3bc/0x3f4) from [<c0296114>] (mmc_wait_for_req+0x208/0x230)
[<c0296114>] (mmc_wait_for_req+0x208/0x230) from [<c02997f8>] (mmc_app_send_scr+0xec/0x134)
[<c02997f8>] (mmc_app_send_scr+0xec/0x134) from [<c02986fc>] (mmc_sd_setup_card+0x20/0x31c)
[<c02986fc>] (mmc_sd_setup_card+0x20/0x31c) from [<c0298f2c>] (mmc_sd_init_card+0x130/0x1d4)
[<c0298f2c>] (mmc_sd_init_card+0x130/0x1d4) from [<c02990e0>] (mmc_attach_sd+0x110/0x198)
[<c02990e0>] (mmc_attach_sd+0x110/0x198) from [<c0295cf8>] (mmc_rescan+0x284/0x30c)
[<c0295cf8>] (mmc_rescan+0x284/0x30c) from [<c006ccb8>] (process_one_work+0x1e4/0x310)
[<c006ccb8>] (process_one_work+0x1e4/0x310) from [<c006d5c0>] (worker_thread+0x1ac/0x2c8)
[<c006d5c0>] (worker_thread+0x1ac/0x2c8) from [<c007132c>] (kthread+0x84/0x8c)
[<c007132c>] (kthread+0x84/0x8c) from [<c003aaf8>] (kernel_thread_exit+0x0/0x8)
Code: e92d4010 e59f000c eb0d8b58 e3a03000 (e5833000)
---[ end trace 8b3ec1ed54497b8d ]---

And this is our configuration.

static struct omap2_hsmmc_info mmc[] = {
   {
#ifdef CONFIG_TI8148EVM_WL12XX
/* WLAN_EN is GP1[21] */
#define GPIO_WLAN_EN   ((1 * 32) + 21)
/* WLAN_IRQ is GP0[30] */
#define GPIO_WLAN_IRQ   ((0 * 32) + 30)
       .mmc       = 1,
       .caps       = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
       .gpio_cd   = -EINVAL,
       .gpio_wp   = -EINVAL,
       .ocr_mask   = MMC_VDD_165_195,
       .nonremovable   = true,
   },
   {
       .mmc        = 2,
#else
       .mmc       = 1,
#endif
       .caps       = MMC_CAP_4_BIT_DATA,
       .gpio_cd   = -EINVAL, /* Dedicated pins for CD and WP */
       .gpio_wp   = -EINVAL,
       .ocr_mask   = MMC_VDD_33_34,
   },
   {
#ifdef CONFIG_TI8148EVM_WL12XX
       .mmc        = 3,
#else
       .mmc       = 2,
#endif
       .caps       = MMC_CAP_4_BIT_DATA,
       .transceiver   = false,
       //.nonremovable   = true,
       .gpio_cd   = -EINVAL, // Dedicated pins for CD and WP
       .gpio_wp   = -EINVAL,
       .ocr_mask   = MMC_VDD_33_34,
   },
   {}   /* Terminator */
};

This is from mmc.h file

#ifdef CONFIG_TI8148EVM_WL12XX
#ifdef CONFIG_MACH_TI8148LPH
#define TI814X_NR_MMC       3
#else
#define TI814X_NR_MMC       2
#endif
#define TI814X_MMC1_BASE   0x48060100 /* TI814X MMC1/SD1 config base */
#define TI814X_MMC1_HL_BASE   0x48060000 /* TI814X HL configuration*/
#define TI814X_MMC2_BASE   0x481D8100 /* TI814X MMC2/SD2 config base */
#define TI814X_MMC2_HL_BASE   0x481D8000 /* TI814X HL configuration*/
#define TI814X_MMC3_BASE    0x47810100 /* TI814X MMC/SD config base */
#define TI814X_MMC3_HL_BASE 0x47810000 /* TI814X HL configuration*/

This is from dma.h

#ifdef CONFIG_TI8148EVM_WL12XX
#define OMAP24XX_DMA_MMC1_TX       24
#define OMAP24XX_DMA_MMC1_RX       25
#else
#define OMAP24XX_DMA_MMC1_RX           3
#define OMAP24XX_DMA_MMC1_TX           2
#endif

#ifdef CONFIG_TI8148EVM_WL12XX
#define OMAP24XX_DMA_MMC2_TX       2
#define OMAP24XX_DMA_MMC2_RX       3
#define OMAP24XX_DMA_MMC3_TX       8
#define OMAP24XX_DMA_MMC3_RX       9
#else
#define OMAP24XX_DMA_MMC2_TX       8   /* E_DMA_MUXED instead of MCASP0TX - SDTXEVT2 */
#define OMAP24XX_DMA_MMC2_RX       9   /* E_DMA_MUXED instead of MCASP0RX - SDRXEVT2 */
#endif

Should something else be configured?

Best regards,

Alexander Vasiljev

over 12 years ago

0 Margarita Gashova over 12 years ago

TI__Guru* 80190 points

Hello,

What is the software release, that you are using here?

Best Regards,

Margarita

0 Alexander Vasiljev over 12 years ago in reply to Margarita Gashova

Expert 1015 points

Hi.

I use ti-ezsdk_dm814x-evm_5_04_00_1. But i have already resolved this issue. For the third mmc another dma defines should be used.

#define OMAP34XX_DMA_MMC3_TX 8
#define OMAP34XX_DMA_MMC3_RX 9

instead of

#define OMAP24XX_DMA_MMC3_TX 8
#define OMAP24XX_DMA_MMC3_RX 9

Best regards,

Alexander Vasiljev.

0 Margarita Gashova over 12 years ago in reply to Alexander Vasiljev

TI__Guru* 80190 points

Hello Alexander,

I am glad that, this issue is solved.

Best Regards,

Margarita

0 hb chen over 12 years ago in reply to Alexander Vasiljev

Expert 2640 points

Dear Sir,

Can you help me figure out what files need to be modified if I want to enable MMC1 and MMC2 (No MMC0) ~

What should be modified in kernel to support MMC2 ?

Here are my changes:

1) mmc.h

+#define TI81XX_NR_MMC 2
-#define TI81XX_NR_MMC 1

+#define TI814X_MMC2_BASE 0x47810100 /* TI814X MMC/SD config base */
+#define TI814X_MMC2_HL_BASE 0x47810000 /* TI814X HL configuration*/

2)board-ti8148evm.c

static struct omap2_hsmmc_info mmc[] = {
   {
       .mmc       = 1, // hbchen , sd card
       .caps       = MMC_CAP_4_BIT_DATA,
+        .gpio_cd   = -EINVAL, // hbchen
-        .gpio_cd   = GPIO_TO_PIN(1, 6), /* Dedicated pins for CD and WP */
       .gpio_wp   = -EINVAL,
       .ocr_mask   = MMC_VDD_33_34,
   },
+    {
+        .mmc       = 2, // hbchen , on board emmc
+        .caps       = MMC_CAP_4_BIT_DATA,
+        .gpio_cd   = -EINVAL,, /* Dedicated pins for CD and WP */
+        .gpio_wp   = -EINVAL,
+        .ocr_mask   = MMC_VDD_33_34,
+    },
   {}   /* Terminator */
};

3) Devices.c : omap2_init_mmc

case 1:
+           if (cpu_is_ti814x()) {
+               base = TI814X_MMC2_BASE;
+             irq = TI814X_IRQ_SD2;
+           }
+           else{
                base = OMAP2_MMC2_BASE;
                irq = INT_24XX_MMC2_IRQ;
+           }
            break;

4) need pinmux for MMC2 ???

5) in dma.h, the original OMAP24XX_DMA_MMC2_TX/OMAP24XX_DMA_MMC2_RX value is 47/48.

Why did you modify it to 8/9 ? or must set to 8/9 ?

Please help ~ thx ~

0 Alexander Vasiljev over 12 years ago in reply to hb chen

Expert 1015 points

Hi, hb.

I was guided by the mmc.rtf document, which was originally posted by one of the TI guys. But i cannot find the original post.

Some changes to region mapping to L3 should be made. So look at mmc section of this document.

4375.MMC.rtf

Best regards,

Alexander Vasiljev.

0 hb chen over 12 years ago in reply to Alexander Vasiljev

Expert 2640 points

Dear Alexander,

Thanks a lot ~

more question ~

The original code of OMAP24XX_DMA_MMC2_TX/OMAP24XX_DMA_MMC2_RX is 47/48,

Do I need to change it to 8/9 ?? ~~ or depend on board ?

Original setting:

#define OMAP24XX_DMA_MMC2_TX       47   /* S_DMA_46 */
#define OMAP24XX_DMA_MMC2_RX       48   /* S_DMA_47 */
==> Your setting
#define OMAP24XX_DMA_MMC2_TX       8
#define OMAP24XX_DMA_MMC2_RX       9

thx ~

0 Alexander Vasiljev over 12 years ago in reply to hb chen

Expert 1015 points

Hi, hb.

As you can see table 8-3, 8-4 (pages 223) in the tms320dm8148d.pdf (i can say only about 8148) SD2 doesn't have default edma events and has only multiplexed events. So we make a dirty hack (as it said in source code) and connect the edma events of SD2 in place of McASP0 (it is ok if you are't going to use McASP0). You can see this dirty hack in arch\arm\mach-omap2\hsmmc.c in function omap2_hsmmc_init. This is described in MMC.rtf. The numbers of McASP0 are 8 and 9. So we use these numbers. It works for me. I use ti-ezsdk_dm814x-evm_5_04_00_11. May be in the latest versions of psp TI guys use not so dirty hack. :)

0 hb chen over 12 years ago in reply to Alexander Vasiljev

Expert 2640 points

Dear Alexander,

Bad news ~ I have to use McASP0 ~ = =" ~

Can MMC2 still work if I don't set DMA Mux for MMC2 ?

May I just follow the original setting ?

#define OMAP24XX_DMA_MMC2_TX 47

#define OMAP24XX_DMA_MMC2_RX 48

thx ~

0 Alexander Vasiljev over 12 years ago in reply to hb chen

Expert 1015 points

Hi, HB.

First of all please read documentation carefully.

I think driver will not work, if you will not set dma mux properly. You can attach SD2 dma events to any event in the table 8-3 in tms320dm8148d.pdf. For example, 47 is for DCAN0, 48 - timer4. Are you going to use them? To mux the dma events you should use registers EDMA3CC_EVTMUX_X_X in control module. They are described from the page 979 (section 3.2.124) in sprugz8c.pdf. So if you want to use 47 and 48, the code in omap2_hsmmc_init should look something like this:

omap_ctrl_writel((TPCC_EVT_MUX_SDTXEVT2<<24), TI814X_CONTROL_TPCC_EVT_MUX_44_47); // 47 for TX

omap_ctrl_writel(TPCC_EVT_MUX_SDRXEVT2, TI814X_CONTROL_TPCC_EVT_MUX_48_51); //48 for RX
omap2_init_mmc(hsmmc_data, TI81XX_NR_MMC);

But i am not quit sure. I recommend you to start new topic and ask how to mux dma events properly.

Best regards,

Alexander Vasiljev.

0 Shunnian Zhai over 12 years ago in reply to Alexander Vasiljev

Intellectual 515 points

Hi, Alexander,

I followed the doc and also your instructions. However, when compiling the code, I got the error on the following two "omap_ctrl_writel", saying " warning: passing argument 2 of 'omap_ctrl_writel' makes integer from pointer without a cast".

omap_ctrl_writel((TPCC_EVT_MUX_SDTXEVT2<<24), TI814X_CONTROL_TPCC_EVT_MUX_44_47); // 47 for TX

omap_ctrl_writel(TPCC_EVT_MUX_SDRXEVT2, TI814X_CONTROL_TPCC_EVT_MUX_48_51); //48 for RXI

Did you encounter this error before? Any idea on how to resolve it?

Thanks and Best Regards,

Shunnian

0 Alexander Vasiljev over 12 years ago in reply to Shunnian Zhai

Expert 1015 points

Hi, Shunnian.

I also encounter this warning. But this is just a warning and i ignore it.

Best regards,

Alexander Vasiljev.

0 Shunnian Zhai over 12 years ago in reply to Alexander Vasiljev

Intellectual 515 points

Hi, Alexander,

Thanks for your reply. I also ignore this warning. Now we managed to make mmc2 work after some HW modifications.

Regards,

Shunnian

0 Vaishnavi Raman over 11 years ago in reply to Shunnian Zhai

Intellectual 430 points

Hi,

I'm working on bringing up wl18xx module in TI8148 + IO expansion daughter card.

I'd set up ti-ezsdk_dm814x-evm_5_05_02_00. I'm using wl18xx compat wireless package.

Since wlan needs MMC0 port, I added MMC0 initilaization in the required files. I've attached the same.

I've installed wl18xx compat wireless packages in the rootfs and I've done insmod too.

root@dm814x-evm:~# cat /proc/modules
wlcore_sdio 3296 0 - Live 0xbf233000
wl18xx 60602 0 - Live 0xbf21a000
wlcore 154048 1 wl18xx, Live 0xbf1e7000
mac80211 288665 2 wl18xx,wlcore, Live 0xbf186000
cfg80211 141666 3 wl18xx,wlcore,mac80211, Live 0xbf153000
compat 10094 5 wlcore_sdio,wl18xx,wlcore,mac80211,cfg80211, Live 0xbf149000
syslink 1133491 0 - Live 0xbf000000

Insmod messages are below.

Compat-wireless backport release: R8.xx_Build-254

Backport based on wl18xx.git R8.xx_Build-309

compat.git: wl18xx.git

cfg80211: Calling CRDA to update world regulatory domain

cfg80211: World regulatory domain updated:
cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp)
cfg80211: (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
cfg80211: (2457000 KHz - 2482000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
cfg80211: (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm)
cfg80211: (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)
cfg80211: (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm)

wlcore: wl18xx driver version: R8.xx_Build-309

Problem:

After insmod of all modules, if I execute,

root@dm814x-evm:~# ifconfig wlan0 up
ifconfig: SIOCGIFFLAGS: No such device

I tried reinserting the modules which didnt help.

1) I doubt the MMC0 initialization. Am I missing something?

2) WLAN_EN pin is high. Anything missing in board file or pin mux?

3) Can you please give detailed steps for wl18xx module in DM814x? Is there any firmware to be loaded or any other commands after inserting the modules?

Please help to resolve this.

Thanks and Regards

Fullscreen 5226.wlan_mmc0_init.txt Download

diff --git a/arch/arm/mach-omap2/board-ti8148evm.c b/arch/arm/mach-omap2/board-ti8148evm.c
index aad6594..8129027 100644
--- a/arch/arm/mach-omap2/board-ti8148evm.c
+++ b/arch/arm/mach-omap2/board-ti8148evm.c
@@ -70,7 +70,20 @@ static struct omap_board_mux board_mux[] __initdata = {

 static struct omap2_hsmmc_info mmc[] = {
        {
-               .mmc            = 1,
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+               .mmc            = 1,
+               .name           = "wl18xx",
+               .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+               .nonremovable   = true,
+               .gpio_cd        = -EINVAL,
+               .gpio_wp        = -EINVAL,
+               .ocr_mask       = MMC_VDD_165_195, /* 3V3 */
+       },
+       {
+               .mmc            = 2,
+#else
+               .mmc            = 1
+#endif
                .caps           = MMC_CAP_4_BIT_DATA,
                .gpio_cd        = -EINVAL, /* Dedicated pins for CD and WP */
                .gpio_wp        = -EINVAL,
				.ocr_mask       = MMC_VDD_33_34,
        },
        {}      /* Terminator */
};

				
#define TI8148EVM_WLAN_IRQ_GPIO                30 /* GP0[30] */
#define TI8148EVM_WL_EN                        47 /* GP1[15] */
#define TI8148EVM_BT_EN                        53 /* GP1[21] */

struct wl12xx_platform_data ti8148evm_wlan_data __initdata = {
        .irq = OMAP_GPIO_IRQ(TI8148EVM_WLAN_IRQ_GPIO),
#ifdef TI8148EVM_WILINK8
        .board_ref_clock = WL12XX_REFCLOCK_38,
        .board_tcxo_clock = WL12XX_TCXOCLOCK_26,
#else
        .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
#endif
        .bt_enable_gpio = TI8148EVM_BT_EN,
        .wlan_enable_gpio = TI8148EVM_WL_EN,
};

static int wl18xx_set_power(struct device *dev, int slot, int on, int vdd)
{
         if (on) {
                gpio_set_value(ti8148evm_wlan_data.wlan_enable_gpio, 1);
                mdelay(70);
         } else {
                gpio_set_value(ti8148evm_wlan_data.wlan_enable_gpio, 0);
         }
         gpio_export(ti8148evm_wlan_data.wlan_enable_gpio, true);
         return 0;
}

static int wl18xx_bluetooth_enable(void)
{
        int status = gpio_request(ti8148evm_wlan_data.bt_enable_gpio,
                "bt_en\n");
        if (status < 0)
                pr_err("Failed to request gpio for bt_enable");

        pr_info("Configure Bluetooth Enable pin...\n");
        gpio_direction_output(ti8148evm_wlan_data.bt_enable_gpio, 1);
        gpio_export(ti8148evm_wlan_data.bt_enable_gpio, true);

        return 0;
}

static void __init wl18xx_init(void)
{
        struct device *dev;
        struct omap_mmc_platform_data *pdata;
        int ret;

        ti8148evm_wlan_data.platform_quirks = WL12XX_PLATFORM_QUIRK_EDGE_IRQ;

        /* Set up mmc0 muxes */
        omap_mux_init_signal("mmc0_clk", TI814X_INPUT_EN | TI814X_PULL_UP);
        omap_mux_init_signal("mmc0_cmd", TI814X_INPUT_EN | TI814X_PULL_UP);
        omap_mux_init_signal("mmc0_dat0", TI814X_INPUT_EN | TI814X_PULL_UP);
        omap_mux_init_signal("mmc0_dat1", TI814X_INPUT_EN | TI814X_PULL_UP);
        omap_mux_init_signal("mmc0_dat2", TI814X_INPUT_EN | TI814X_PULL_UP);
        omap_mux_init_signal("mmc0_dat3", TI814X_INPUT_EN | TI814X_PULL_UP);

        omap_mux_init_signal("gpio1_15_mux1", TI814X_PULL_UP);
        omap_mux_init_signal("gpio1_21", TI814X_PULL_UP);
        omap_mux_init_signal("gpio0_30", TI814X_INPUT_EN | TI814X_PULL_DIS);

        wl18xx_bluetooth_enable();

        if (wl12xx_set_platform_data(&ti8148evm_wlan_data))
                pr_err("error setting wl18xx data\n");

        ret = gpio_request_one(ti8148evm_wlan_data.wlan_enable_gpio,
                GPIOF_OUT_INIT_LOW, "wlan_en");
        if (ret) {
                pr_err("Error requesting wlan enable gpio: %d\n", ret);
                goto out;
        }

        dev = mmc[0].dev;
        if (!dev) {
                pr_err("wl18xx mmc device initialization failed\n");
				goto out;
        }

        pdata->slots[0].set_power = wl18xx_set_power;

out:
        return;
}

@@ -937,6 +968,7 @@ static void __init ti8148_evm_init(void)
        __raw_writel(0x0, DSS_HDMI_RESET);
        platform_add_devices(ti8148_devices, ARRAY_SIZE(ti8148_devices));
 #endif
+       wl18xx_init();
        regulator_use_dummy_regulator();
        board_nor_init(ti814x_evm_norflash_partitions,
                ARRAY_SIZE(ti814x_evm_norflash_partitions), 0);

				
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c164c91..b698868 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -1074,13 +1074,20 @@ void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
                                base = TI816X_MMC1_BASE;
                                irq = TI81XX_IRQ_SD;
                        } else if (cpu_is_ti814x()) {
+                               printk("*******%d: %s mmc1 base\n", __LINE__, __func__);
                                base = TI814X_MMC1_BASE;
-                               irq = TI814X_IRQ_SD1;
+                               irq = TI81XX_IRQ_SD;
                        }
                        break;
                case 1:
-                       base = OMAP2_MMC2_BASE;
-                       irq = INT_24XX_MMC2_IRQ;
+                       if (cpu_is_ti814x()) {
+                               printk("*******%d: %s mmc2 base\n", __LINE__, __func__);
+                               base = TI814X_MMC2_BASE;
+                               irq = TI814X_IRQ_SD1;
+                       } else {
+                               base = OMAP2_MMC2_BASE;
+                               irq = INT_24XX_MMC2_IRQ;
+                       }
                        break;
                case 2:
                        if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
		
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 3795238..7f8675b 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -206,6 +206,8 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,

 #ifndef CONFIG_ARCH_TI81XX
 static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
+#elif defined CONFIG_ARCH_TI814X
+static struct omap_mmc_platform_data *hsmmc_data[TI814X_NR_MMC] __initdata;
 #else
 static struct omap_mmc_platform_data *hsmmc_data[TI81XX_NR_MMC] __initdata;

 @@ -376,6 +383,10 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)

        if (!cpu_is_ti81xx())
                omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
+       else if (cpu_is_ti814x()) {
+               printk("*********%d: %s: ti814x omap init\n", __LINE__, __func__);
+               omap2_init_mmc(hsmmc_data, TI814X_NR_MMC);
+       }
        else
                omap2_init_mmc(hsmmc_data, TI81XX_NR_MMC);

diff --git a/arch/arm/plat-omap/include/plat/dma.h b/arch/arm/plat-omap/include/plat/dma.h
index 6e02755..66180c1 100644
--- a/arch/arm/plat-omap/include/plat/dma.h
+++ b/arch/arm/plat-omap/include/plat/dma.h
@@ -185,9 +185,14 @@
 #define OMAP24XX_DMA_SPI1_TX3          52      /* E_DMA_52 */
 #define OMAP24XX_DMA_SPI1_RX3          53      /* E_DMA_53 */

+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#define OMAP24XX_DMA_MMC1_TX           24
+#define OMAP24XX_DMA_MMC1_RX           25
+#else
 #define OMAP24XX_DMA_MMC1_RX           3
 #define OMAP24XX_DMA_MMC1_TX           2
 #endif
+#endif

 #else
 #define OMAP24XX_DMA_SPI1_TX0          35      /* S_DMA_34 */
@@ -215,8 +220,13 @@
 #define OMAP24XX_DMA_SPI2_TX1          45      /* S_DMA_44 */
 #define OMAP24XX_DMA_SPI2_RX1          46      /* S_DMA_45 */
 #endif
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#define OMAP24XX_DMA_MMC2_TX           2 //8 /* 2 */
+#define OMAP24XX_DMA_MMC2_RX           3 //9 /* 3 */
+#else
 #define OMAP24XX_DMA_MMC2_TX           47      /* S_DMA_46 */
 #define OMAP24XX_DMA_MMC2_RX           48      /* S_DMA_47 */
+#endif /* CONFIG_WL12XX_PLATFORM_DATA */
 #define OMAP24XX_DMA_UART1_TX          49      /* S_DMA_48 */
 #define OMAP24XX_DMA_UART1_RX          50      /* S_DMA_49 */
 #define OMAP24XX_DMA_UART2_TX          51      /* S_DMA_50 */

 diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 1d9ff36..b518825 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -36,12 +36,19 @@
 #define OMAP4_MMC5_BASE                0x480d5000
 #define OMAP4_MMC_REG_OFFSET   0x100

+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+#define TI814X_NR_MMC          2
+#else
+#define TI814X_NR_MMC          1
+#endif
 #define TI81XX_NR_MMC          1
 #define TI81XX_HSMMC_SIZE      0x10000
 #define TI816X_MMC1_BASE       0x48060100 /* TI816X MMC/SD config base */
 #define TI816X_MMC1_HL_BASE    0x48060000 /* TI816X HL configuration*/
-#define TI814X_MMC1_BASE       0x481D8100 /* TI814X MMC/SD config base */
-#define TI814X_MMC1_HL_BASE    0x481D8000 /* TI814X HL configuration*/
+#define TI814X_MMC1_BASE       0x48060100 /* TI814X MMC1/SD1 config base */
+#define TI814X_MMC1_HL_BASE    0x48060000 /* TI814X HL configuration*/
+#define TI814X_MMC2_BASE       0x481D8100 /* TI814X MMC2/SD2 config base */
+#define TI814X_MMC2_HL_BASE    0x481D8000 /* TI814X HL configuration*/

 #define HSMMC5                 (1 << 4)
 #define HSMMC4                 (1 << 3)

Vaishnavi

0 Margarita Gashova over 11 years ago in reply to Vaishnavi Raman

TI__Guru* 80190 points

Hello Vaishnavi,

You could check Vladimir's reply here:

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/193927/701096.aspx

Hope this help.

Best Regards,

Margarita

0 Vaishnavi Raman over 11 years ago in reply to Margarita Gashova

Intellectual 430 points

Hello Margarita,

I can't find a solution from the link specified.

I've probed the signals and MMC0 clock is not coming out.

There is some problem in MMC0 initialization. Also I doubt the parameters passed in structure omap_mmc_platform_data of board file.

Can you please help in initializing MMC0 for DM814x? I've attached the files in previous post.

Thanks and Regards
Vaishnavi

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