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AM3517 Display Subsystem Pixel clock

g.f.
Guru 15520 points
Other Parts Discussed in Thread: AM3517

Hi,

I'm having a problem with AM3517 Display Subsytem.
I'm using TI Linux Video Driver, and setting pixel clock like follow:

/*XGA 1024x768@60Hz*/
static struct omap_video_timings sff792_xga_timings =
{ .x_res = 1024, .y_res = 768, .pixel_clock = 65000, .hfp = 24, .hsw = 136, .hbp = 160, .vfp = 3, .vsw = 6, .vbp = 29, };

Display resolution : 1024x768
Frame refresh rate : 60Hz
Vertical visible pixel : 768 lines
Vertical front porch : 3 lines
Vertical sync : 6 lines
Vertical back porch : 3 lines
Horizontal visible pixel : 1024 columns
Horizontal front porch : 24 columns
Horizontal sync : 136 columns
Horizontal back porch : 160 columns

I was thinking that pixel clock will be 65MHz by the above setting,
but when I checked the output the pixel clock was about 62MHz.

Is there anyway to set the pixel clock to 65MHz?

best regards,
g.f.

  • 0
    Guru 31670 points

    In the structure VBP is 29 and in the logs VBP is 3 lines. Adjust VBP properly to get 65MHz. But why are you particular about 65MHz if you are getting the expected refresh rate?

  • 0 in reply to Renjith Thomas
    Guru 15520 points

    Renjith,

    Thank you for response.

    The following is not log, but its details of the setting in the video driver.
    **********************************************************
    Display resolution : 1024x768
    Frame refresh rate : 60Hz
    Vertical visible pixel : 768 lines
    Vertical front porch : 3 lines
    Vertical sync : 6 lines
    Vertical back porch : 29 lines(Sorry, it's not 3 but 29)
    Horizontal visible pixel : 1024 columns
    Horizontal front porch : 24 columns
    Horizontal sync : 136 columns
    Horizontal back porch : 160 columns
    **********************************************************

    When we calculate from the setting, it will be like follow:
    (I refer to AM3517 TRM page.1427 12.6.3.3.1 for calculation)
    Total frame pixel count = (768 + 3 + 6 + 29) x (1024 + 24 + 136 + 160)
                            = 1083264 pixel
    Pixel clock Frequency = 1083264 x 60 Hz
                          = 64.99 MHz

    So, I thought the pixel clock output will be 65MHz..

    best regards,

    g.f

  • 0 in reply to g.f.
    Guru 31670 points

    GF,

    Did you probe the VSYNC line? What is the frequency that you are seeing? Is it 60fps or slightly less (58/59Hz)?

    Also can you check the value of the DISPC_DIVISIOR? See the code where this register is getting set and see what is the reference clock used for calculating the value?

  • 0 in reply to Renjith Thomas
    Guru 15520 points

    Hi Renjith,

    Thank you for response.

    Actually this question was from our customer, so I don't know the detail.
    I will tell our customer to probe the VSYNC line and what is the frequency.

    By the way, the structure which I post, I guess it is for the refresh rate determination.
    So, setting the pixel_clock to 65000 in the structure, actually pixel clock is not set up in fact.
    Am I right?

    I will ask our customer to check the value of the DISPC_DIVISOR.
    If you know the Linux SDK code where this register is getting set,
    can you please tell me the place where I can find it.
    I'm looking at ti-sdk-am3517-evm-4.0.1.0, but I can't find it.

    best regards,
    g.f.

  • 0 in reply to g.f.
    Guru 31670 points

    GF,

    The pixel clock can be set using the variable, but practically it may not set the exact values as divisors does support only integer divisors. A quick work around what I will recommend it to slightly increase the pixel clock to 66or 67MHz and see what is the pixel clock value set. If you are interested in finding the exact issue, you've to calculate the PLLs involved in generating the pixel clock.

  • 0 in reply to Renjith Thomas
    Guru 15520 points

    Hi Renjith,

    Thank you so much.
    I understood.

    best regards,
    g.f.