C6415 Device cycle accurate simulator

Hi:

I 'm using C6415 Device cycle accurate simulator to cachetune my project,  I know if from datashit that the L1D of C6415 is 16KB, and I set L2 64 KB ram, when I place four arrays: char data0[0x1000] ,data1[0x1000] ,data2[0x1000] ,data3[0x1000] on DDR2, and cachetune it, it will be all L1D.miss.read form the graph, but when I place these four arrays on L2 RAM, it will have L1D.hit, why? Could you help me with this problem?

the code is as follows:

#define LEN 0x100

 #pragma DATA_SECTION(data1,".mydata")

#pragma DATA_SECTION(data2,".mydata")

#pragma DATA_SECTION(data3,".mydata")

 #pragma DATA_SECTION(data4,".mydata")

char data1[LEN];

char data2[LEN];

char data3[LEN];

char data4[LEN];

 int main()

 {

 int i,j,k;  

for( i = 0; i < LEN; i++ )  

{   data1[i] = 1;   data2[i] = 1;  }

 for( i = 0; i < LEN; i++ )  

{   data3[i] = 1;   data4[i] = 1;  }

 for( i = 0; i < LEN; i++ )  

{   data3[i] = 1;   data4[i] = 1;  }

  for( i = 0; i < LEN; i++ )  

 {    k = data1[i] ;    k = data2[i] ;    k = data3[i] ;    k = data4[i] ;   }

 for( i = 0; i < LEN; i++ )  

{   k = data1[i] ;   k = data2[i] ;   k = data3[i] ;   k = data4[i] ;  }

 return 0;

 }

and the cmd is :

MEMORY

 {

 L2RAM:     o = 0x00000000  l = 0x00010000 /* 64K L2 RAM */    

 DDR2:      o = 0x80000000    l = 0x10000000   /* 256 MBytes */

} 

SECTIONS

{  

.vectors        >       DDR2    

 .text           >       DDR2    

.stack          >       DDR2   

  .far            >       DDR2    

.switch         >       DDR2    

  .data           >       DDR2    

.bss            >       DDR2    

 .const          >       DDR2    

 .sysmem         >    DDR2

.mydata         >       DDR2

}