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C6678 emulator reset line

Mark Purcell2
Prodigy 20 points
Other Parts Discussed in Thread: TMS320C6678

Hi All,

We have a TMS320C6678 board which has an emulator connector

What exactly should we do with the emulator's reset line? It's unclear whether this is a reset to the DSP, or from other logic on board to the emulator. The EVM (I think, from reading the verilog FPGA code) appears to generate a soft reset, i.e. assert RESETn, to the DSP, although I cannot see any transitions on the emulator reset at all while debugging. There's no timing information regarding this that I can find.

We have a board that seems flaky with Code Composer during debugging and one symptom is the emulator cannot reset cores reliably. Any help appreciated.

Mark.

  • 0
    TI__Mastermind 46460 points

    Mark,

    The emulator connector's target reset line is intended to be a reset for the entire board if it is implemented.  However, it is optional and at the board designer's discretion.  The SPRU655 document explains it in more detail.

    Emulation control through the JTAG port supports CPU core resets.  This support is consistent across all board implementations.

    The C6678 EVM drives the RESETz low and high again when the target reset is triggered.  This will have the same affect as pushing the Warm Reset button.  Do you see the same results?  Note that RESETz does not latch boot config and it can be blocked internally based on register configuration.

    Tom