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OMAP-L138 SCR priority handling

Muf
Expert 4590 points
Other Parts Discussed in Thread: OMAP-L138

Hello,

I have a few questions related to OMAP-L138 Switched Central Resource priority handling (section 11.3. from TRM - SPRUH77A) . Could you help to clarify that?

1. Mechanism based on which the OMAP-L138 generated EMIFA requests:

If Code Composer generates instructions to move an array of 100 16-bit words from NOR Flash to SRAM, will the SCR controller generate 100 16-bit individual EMIFA requests, or will the SRC be busy with a single EMIFA request comprising the entire array?

2. Please clarify whether an SCR master with a high priority can interrupt a pending low priority EMIFA request.

3. Please indicate how-whether the device allows configuring a transfer length for an EMIFA request after which another SCR master can take control over the SCR before the entire transfer is completed.

Thanks and best regards,
Roman.

  • 0
    TI__Guru* 83985 points

    Roman

    The concept and details for system interconnect have been provided on the following wiki article

    http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_SoC_Architectural_Overview

    Have you looked at this? If not, I recommend spending some time reading this and after that whatever follow up questions arise specific to EMIFA or SCR interaction, we can try and further clarify.

    Regards

    Mukul

  • 0
    TI__Expert 7470 points

    Roman,

    Muf said:
    If Code Composer generates instructions to move an array of

    A bit confused about above question. Do you mean a memory fill option etc. from a CCS window or do you actually mean CPU reads in a user program? I assume it is the latter.

    Muf said:
    1. Mechanism based on which the OMAP-L138 generated EMIFA requests

    Yes, 100 requests will be generated through the SCR since these are essentially individual data read requests in software and system cannot send these as bursts.

    Muf said:
    2. Please clarify whether an SCR master with a high priority can interrupt a pending low priority EMIFA request.

    A higher priority request takes precedence over a lower-priority request for access to the SCR (or round-robin if same priority level). However, once a request has been queued in a bridge FIFO at the other end of an SCR, a new request being queued in the bridge FIFO cannot pre-empt the pending request even if the new request if higher priority.

    Muf said:
    3. Please indicate how-whether the device allows configuring a transfer length for an EMIFA request after which another SCR master can take control over the SCR before the entire transfer is completed.

    A burst transfer is an indivisible atomic transaction - the burst sizes for different masters are described in the wiki. The priority-level or round-robin arbitration happens on a burst boundary and not a transfer-length boundary - so essentially a higher (or same) priority request from a different master can submit it's transaction request before another lower (or same) priority request can complete its transfer length. Setting the priorities appropriately is a system-level exercise and is based on the customer use-case.

    Hope this answers your questions.

    Regards,

    Sunil Kamath