About the MSI interrupt generation in PCIe EP Mode of DM8168.

RY,

Your understanding on "outbound transaction" is needed to generate MSI is correct.

Step 6 is really an extension of step 5 where it means that the outbound write can go through address translation if required.

Consider 2 cases as example:

A) MSI generation w/ address translation -- this is most likely use case

1. RC sets MSI address (in EP side register) as 0x60000010
2. EP side s/w sets outbound translation window size as 8MB each and first window translation for 0x60000000 (i.e., 0x20000000 = 0x60000000 over PCIe)
3. EP s/w issues a write transaction to address 0x20000010 with MSI data to generate MSI on RC
4. The above write goes as address translated to 0x60000010 over PCIe and lands on RC side, in turn, generates interrupt

B) MSI generation w/o address translation

1. RC sets MSI address (in EP side register) as 0x00000010
2. EP s/w issues a write transaction to address 0x20000010 with MSI data to generate MSI on RC
3. The above write goes as address un-translated with MS 4 bits masked (28-bit address range = 256 MB side) as 0x00000010 over PCIe and lands on RC side, in turn, generates interrupt

As you can see, case A corresponds to step 6, while B is closer to step 5, but I would say the description in TRM should instead mention that the write transaction should be at offset same as MSI address from base of outbound window (0x20000000 + MSI address).

Note, as we know, in both of the above cases, we have to use one outbound window region to be able to generate MSI and thus I would rather recommend method A where outbound translations are configured always.