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what's the state of RSTOUTn pin of dm8168 during power up?

Hi.

I am confused of the state of RSTOUTn pin of dm8168 during power up. 

In sprs614c(DM8168 data sheet), it is said that " the RSTOUT pin on the device reflects device reset status and is de-asserted(high) when the device is out of reset. In addition, this output is always 3-stated and the internal pull resistor is disabled on this pin while POR or RESET is asserted; therefore, an external pull up or pull down can be used to set the state of this pin(high or low) while POR or RESET is asserted. "

In our design, we need RSTOUTn to be a pulse(high to low to high) rather than a rising edge(low to high). It seems that if we use a pull up resistor on RSTOUTn, we can ensure RSROUTn signal  to be high for sometime(during RSTOUTn is 3-stated).But in fact ,we didn't get a pulse although a pull up resistor.

What's more, in DM8148 data sheet, it illustrates that RSTOUT_WD_OUT is Hi-Z during power up for sometime but it does not in DM8168 data sheet.

So I want to know whether and when RSTOUTn is Hi-Z during power up, and how can I get a pulse(high to low to high) on RSROUTn?

  

Thank you.

Regards,

Sean

  • Hi Sean,

    You can get a pulse on the RSTOUTn pin, when any of the following resets occur:

    • Power-On Reset (POR)
    • External Warm Reset
    • Emulation Warm Reset (RESET)
    • Software Global Cold/Warm Reset
    • Watchdog Timer Reset

    The RSTOUTn pin on the device reflects the device reset status. The RSTOUTn pin remains asserted until the PRCM module releases the host ARM Cortex-A8 processor for reset. This output is always asserted when any of the above resets occur.

    Thus you can generate a pulse entirely by SW, using the Software Global Cold/Warm Reset. Software initiates a software global cold reset by writing to RST_GLOBAL_COLD_SW in the PRM_RST_CTRL register. Software initiates a software global warm reset by writing to RST_GLOBAL_WARM_SW in the
    PRM_RST_CTRL register.

    The RSTOUTn pin is de-asserted (high) when the device is out of reset. In addition, this output is always 3-stated and the internal pull resistor is disabled on this pin
    while POR or RESET is asserted; therefore, an external pullup or pulldown can be used to set the state of this pin (high or low) while POR or RESET is asserted.

    When any reset (other than test reset) is asserted, all device pins are put into a Hi-Z state except for emulation pins and RSTOUTn pin.

    Regards,

    Pavel