MIPI DSI BTA data

wu william

Intellectual 460 points

Other Parts Discussed in Thread: SYSCONFIG

Hi~

We have used PandaBoard ES .

We have use "dsi_vc_gen_read_2" to read data from panel.

When "dsi_vc_send_bta_sync" send BTA is always get error here.

[    6.885589] omapdss DSI: dsi_vc_send_bta 0
[   11.934661] [<c0019cf8>] (unwind_backtrace+0x0/0xf8) from [<c030a504>] (omap_dsi_irq_handler+0x120/0x33c)
[   11.944824] [<c030a504>] (omap_dsi_irq_handler+0x120/0x33c) from [<c0082274>] (handle_irq_event_percpu+0x6c/0x2b8)
[   11.944824] [<c0082274>] (handle_irq_event_percpu+0x6c/0x2b8) from [<c00824fc>] (handle_irq_event+0x3c/0x5c)
[   11.944824] [<c00824fc>] (handle_irq_event+0x3c/0x5c) from [<c0084e98>] (handle_fasteoi_irq+0x98/0x140)
[   11.944824] [<c0084e98>] (handle_fasteoi_irq+0x98/0x140) from [<c0081adc>] (generic_handle_irq+0x30/0x44)
[   11.986297] [<c0081adc>] (generic_handle_irq+0x30/0x44) from [<c0013c78>] (handle_IRQ+0x4c/0xac)
[   11.986297] [<c0013c78>] (handle_IRQ+0x4c/0xac) from [<c062c5b4>] (__irq_svc+0x34/0xac)
[   11.986297] [<c062c5b4>] (__irq_svc+0x34/0xac) from [<c02c45d0>] (__delay+0x0/0xc)

But waveform have feedback value in scope.

Got RX Fifo is empty error. data haven't save to register?

RX fifo empty when trying to read.\n");

0x54 is the value we wanted.

0x11 is very strange here. this filed is Data type? or others ?

We used ILI9486 panel and sent 0xDAH , return 0x87 0x11 0x54 0x00 0x36

according DSI Short packet format , data 1 => 0x54 data2 =>0x00, match SPEC.

val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
DSSDBG("\theader: %08x\n", val);

[ 16.845489] omapdss DSI: header: 00000000
[ 16.845489] omapdss DSI error: unknown datatype 0x00

[   11.528167] DSI_REVISION                        00000030
[   11.536407] DSI_SYSCONFIG                       00000011
[   11.536407] DSI_SYSSTATUS                       00000001
[   11.536407] DSI_IRQSTATUS                       00000000
[   11.547607] DSI_IRQENABLE                       0015c000
[   11.558898] DSI_CTRL                            00eaea99
[   11.558898] DSI_COMPLEXIO_CFG1                  6a000021
[   11.558898] DSI_COMPLEXIO_IRQ_STATUS            00000000
[   11.575683] DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
[   11.575683] DSI_CLK_CTRL                        a0346009
[   11.575683] DSI_TIMING1                         7fff7fff
[   11.592498] DSI_TIMING2                         ffff7fff
[   11.592498] DSI_VM_TIMING1                      0001406c
[   11.592498] DSI_VM_TIMING2                      04030c02
[   11.609283] DSI_VM_TIMING3                      048f01e0
[   11.609283] DSI_CLK_TIMING                      00001712
[   11.620483] DSI_TX_FIFO_VC_SIZE                 13121110
[   11.620483] DSI_RX_FIFO_VC_SIZE                 13121110
[   11.620483] DSI_COMPLEXIO_CFG2                  00020000
[   11.637268] DSI_RX_FIFO_VC_FULLNESS             00000000
[   11.637268] DSI_VM_TIMING4                      00487296
[   11.637268] DSI_TX_FIFO_VC_EMPTINESS            1f1f1f1f
[   11.654052] DSI_VM_TIMING5                      0082df3b
[   11.654052] DSI_VM_TIMING6                      7a6731d1
[   11.659759] DSI_VM_TIMING7                      0012000f
[   11.659759] DSI_STOPCLK_TIMING                  00000080
[   11.676544] DSI_VC_CTRL(0)                      20808d81
[   11.676544] DSI_VC_TE(0)                        00000000
[   11.676544] DSI_VC_LONG_PACKET_HEADER(0)        00000000
[   11.693328] DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
[   11.693328] DSI_VC_SHORT_PACKET_HEADER(0)       00000000
[   11.693328] DSI_VC_IRQSTATUS(0)                 00000000
[   11.710113] DSI_VC_IRQENABLE(0)                 000000db
[   11.710113] DSI_VC_CTRL(1)                      20808d81
[   11.710113] DSI_VC_TE(1)                        00000000
[   11.726898] DSI_VC_LONG_PACKET_HEADER(1)        00000000
[   11.726898] DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
[   11.726898] DSI_VC_SHORT_PACKET_HEADER(1)       00000000
[   11.738098] DSI_VC_IRQSTATUS(1)                 00000000
[   11.738098] DSI_VC_IRQENABLE(1)                 000000db
[   11.738098] DSI_VC_CTRL(2)                      20808d81
[   11.754882] DSI_VC_TE(2)                        00000000
[   11.760589] DSI_VC_LONG_PACKET_HEADER(2)        00000000
[   11.760589] DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
[   11.760589] DSI_VC_SHORT_PACKET_HEADER(2)       00000000
[   11.777374] DSI_VC_IRQSTATUS(2)                 00000000
[   11.777374] DSI_VC_IRQENABLE(2)                 000000db
[   11.777374] DSI_VC_CTRL(3)                      20808d81
[   11.794158] DSI_VC_TE(3)                        00000000
[   11.794158] DSI_VC_LONG_PACKET_HEADER(3)        00000000
[   11.810943] DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
[   11.810943] DSI_VC_SHORT_PACKET_HEADER(3)       00000000
[   11.810943] DSI_VC_IRQSTATUS(3)                 00000000
[   11.827728] DSI_VC_IRQENABLE(3)                 000000db
[   11.827728] DSI_DSIPHY_CFG0                     0f22101b
[   11.838928] DSI_DSIPHY_CFG1                     42050d2f
[   11.838928] DSI_DSIPHY_CFG2                     b800000c
[   11.838928] DSI_DSIPHY_CFG5                     e3000000
[   11.855712] DSI_PLL_CONTROL                     00000000
[   11.855712] DSI_PLL_STATUS                      00000383
[   11.867004] DSI_PLL_GO                          00000000
[   11.867004] DSI_PLL_CONFIGURATION1              14a12c1f
[   11.867004] DSI_PLL_CONFIGURATION2              00656008

Could you help us to resolved this problem?

thank you.

over 12 years ago

0 wu william over 12 years ago

Intellectual 460 points

Hi~~

I found a very strange situation here.

int dsi_vc_gen_read_2(struct omap_dss_device *dssdev, int channel, u16 cmd,
u8 *buf, int buflen)
{

................

r = dsi_vc_send_bta_sync(dssdev, channel);
if (r)
  goto err;
printk("Header = %x\n",dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)));  // We can read back value here 0x3b005411
/* RX_FIFO_NOT_EMPTY */
/* if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
  DSSERR("RX fifo empty when trying to read.\n");
  r = -EIO;
  goto err;
}*/

//printk("Header = %x\n",dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)));

//val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));

................

}

int dsi_vc_gen_read_2(struct omap_dss_device *dssdev, int channel, u16 cmd,
u8 *buf, int buflen)
{

................

r = dsi_vc_send_bta_sync(dssdev, channel);
if (r)
  goto err;
//printk("Header = %x\n",dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)));   /* RX_FIFO_NOT_EMPTY */
/* if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
  DSSERR("RX fifo empty when trying to read.\n");
  r = -EIO;
  goto err;
}*/

printk("Header = %x\n",dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel))); // can/t read back value here 0x00000000

//val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));

................

}

am I miss some settings here ??

0 Rafael Rodriguez over 12 years ago in reply to wu william

TI__Intellectual 1035 points

Hi Wu

On a quick look on your register dump, you do not have enabled the interrupt BTA_IRQ_EN on the register DSI_VC_IRQENABLE_i[5].

The function dsi_vc_send_bta_sync is waiting for this interrupt to occur.

Also enable PACKET_SENT_IRQ_EN in the register DSI_VC_IRQENABLE_i[2

For more info check the TRM section 10.3.4.4.8 Bus Turnaround

Regards

Rafael.

Processors

Processors forum

MIPI DSI BTA data