LCD pixel clock configure

yuanjun ren

Intellectual 730 points

Other Parts Discussed in Thread: DM3730

Hi,all

processor:DM3730

Which registers can I configure to determine the LCD pixel clock in DM3730? How to select DSS' ICLK and FCLK?

over 13 years ago

0 Renjith Thomas over 13 years ago

Guru 31670 points

Ren,

Check the register DISPC_DIVISOR where you can divide and configure the appropriate pixel clock based on the DSS function clock. For detailed information about the interface/function clocks for DSS please check the section 3.5.3.4.2 "Clock Distribution Summary" in the latest DM3730 TRM.

0 yuanjun ren over 13 years ago in reply to Renjith Thomas

Intellectual 730 points

Hi, Renjith Thomas

Thank you for your reply, I want to use DPLL4_ALWON_FCLK for function clock, but I don't know how to configure DPLL4_ALWON_FCLK. Is the DPLL4_ALWON_FCLK 864Mhz?

0 yuanjun ren over 13 years ago in reply to yuanjun ren

Intellectual 730 points

How lock the DPLL4 at 865Mhz?

0 Renjith Thomas over 13 years ago in reply to yuanjun ren

Guru 31670 points

Ren,

Why do you need such a high clock? I'm not sure whether you can get such a high and stable clock for DSS.

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LCD pixel clock configure