DM814x DPLLLJ documentation for PTP implementation

Andrew Elder

Looking at Section 2.6.7 "M2 & N2 Change On-the-Fly" SPRUGZ8B (TMS320DM814x TRM), it is clearly stated that M2 & N2 can be updated and the clock period will switch "cleanly" to the new rate.

The PTP implementation described here <http://processors.wiki.ti.com/index.php/TI81XX_PSP_Ethernet_Switch_User_Guide#IEEE_1588.2F802.1AS_PTP_Support>

uses this code here

 <http://arago-project.org/git/projects/?p=linux-omap3.git;a=blob;f=arch/arm/mach-omap2/adpll_ti814x.c;h=473a7ab2b74ec819d16f50c790db206b55369f40;hb=84a34fba9ad4cc00736ad577893f87a3d0f10e19#l937>

to adjust fractional M.

The TRM does not specify what happens to the DPLLLJ output
when fractional M is updated. What is the specified behaviour?
Better yet, what are the recommended  software steps to have
a DPLLLJ clock output "follow" an external clock source.
The approach used by PTP is not supported at all be the documentation in the TRM.

Thanks,
Andrew

over 13 years ago

0 Vladimir-XID over 13 years ago

TI__Genius 11470 points

Hello,

I will try to involve someone here to help.

Vladimir

0 Andrew Elder over 13 years ago in reply to Vladimir-XID

Expert 1680 points

Thank you. When might I hope to see a response?

- Andrew

0 Andrew Elder over 13 years ago in reply to Andrew Elder

Expert 1680 points

Any updates?

0 Vladimir-XID over 13 years ago in reply to Andrew Elder

TI__Genius 11470 points

Hello,

They are working on this. I hope that there will be an answer soon. Sorry for the delay. Thank you.

Vladimir

0 Andrew Elder over 13 years ago in reply to Vladimir-XID

Expert 1680 points

Thank you for the update.

0 Andrew Elder over 13 years ago in reply to Vladimir-XID

Expert 1680 points

Hi Vladimir,

We are trying to make some design decisions before going to board layout, so need some answers soon.

Just to elaborate further, what is the effect of writing to M integer followed by M factional? They are obviously not atomic operations, so how is the PLL specified to behave? If M factional is at the upper edge of it's range, a small change make cause M to increment and M fractional to go to zero. What happens to the PLL output in that case?

Thanks,

Andrew

0 Vladimir-XID over 13 years ago in reply to Andrew Elder

TI__Genius 11470 points

Hello Andrew,

I am really sorry for that big delay. Apparently they are facing some difficulties acquiring this information. I personally cannot give the answers. I will escalate that again. Please, tell me the name of your local field engineer.

Vladimir

0 Andrew Elder over 13 years ago in reply to Vladimir-XID

Expert 1680 points

Jace H. Hall out of Dallas, TX

0 Vladimir-XID over 13 years ago in reply to Andrew Elder

TI__Genius 11470 points

Hello Andrew,

You will receive information from your FAE. Thank you.

Vladimir

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DM814x DPLLLJ documentation for PTP implementation