Hi
I've got a nasty one here.
With the exact same board and code (same binary actually), we have a C6745 rev 2.0 that works fine and a C6745 rev 2.1 that errors out with
Assertion failed, (0 != timeout), file Mcasp.c, line 3777
soon after startup.
We have 5 identical custom boards using the C6745 for a multi-channel audio application. We're using multi-channel codecs and communicating with the DSP on McASP 1. This is our 2nd iteration of this board design, so we are sure it should work. The first board was populated separately as a test. When we tested it and were satisfied that it worked fine, we ordered more parts and had the rest populated.
Because it was a different order, the first board was populated with a C6745 rev 2.0. On the chip is printed:
TMS320
C6745BPTP3
YF-07AK4ZW G4
538 PTP
This DSP works fine.
The later boards happened to get C6745 rev 2.1s. On the chip is printed:
TMS320
C6745CPTP3
YF-21A1YZW G4
21 538 PTP
After about 30 sec of not transmitting any audio and showing 0% CPU usage after setting up their network ports, these DSPs error out with "Assertion failed, (0 != timeout), file Mcasp.c, line 3777" and the McASPs never work. No audio is ever transmitted. If i remove that assertion code in mcasp.c, i eventually get another ("Assertion failed, (0 != timeout), file Mcasp.c, line 3892"). This happens on all boards with the rev 2.1 C6745.
We're using PSP Drivers 1.30.01. Our board design is based off of the OMAP L-137 EVM from Spectrum Digital.
I've tried compiling with CCSv3.3 using older the code gen tools and DSP/BIOS with which we began development, and CCv4 using up to date code gen tools, etc, but both fail on the rev 2.1 chips and run fine on rev 2.0. The only difference i could find in the silicon errata that should affect us is
2.1.3 Clock Input Buffers Updated for Noise Immunity
For silicon revision 2.1, the I/O buffers for all McASP clock inputs have been improved to provide more
robust noise immunity than in previous silicon revisions. Timing specifications are not affected as a result.
In particular, the specification for maximum input transition time remains the same; the improvements
simply provide more margin to the existing specification.
We are not using USB on this board, which is what the other changes in rev 2.1 seem to be about.
It is still possible that some other component on the newer populated boards is malfunctioning, but we have yet to find one.
Any thoughts? What can we do? Have the McASPs changed in the processor rev?
Thanks,
Arvid
Edit: here are the printouts from the C6747 Diagnostic GEL file. How do i interpret the differences between these? Obviously the bootloader is different so i need to start using AISgen for d800k005, but the problem happens during emulation, not just when self booting from flash.
Rev 2.0 before load: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | Device Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: DEV_INFO_00 = 0x9B7DF02F C674X_0: GEL Output: DEV_INFO_01 = 0x00000000 C674X_0: GEL Output: DEV_INFO_02 = 0x0000FB75 C674X_0: GEL Output: DEV_INFO_03 = 0x00000002 C674X_0: GEL Output: DEV_INFO_04 = 0x00000000 C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0 C674X_0: GEL Output: DEV_INFO_06 = 0x00000080 C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 8-0-151387-7-10-33 C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 0,0,0,9177 C674X_0: GEL Output: ----- C674X_0: GEL Output: DEV_INFO_17 = 0x00030003 C674X_0: GEL Output: DEV_INFO_18 = 0x00000000 C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: C674X_0: GEL Output: ----- C674X_0: GEL Output: DEV_INFO_20 = 0x30303864 C674X_0: GEL Output: DEV_INFO_21 = 0x3330306B C674X_0: GEL Output: DEV_INFO_22 = 0x00000000 C674X_0: GEL Output: DEV_INFO_23 = 0x00000000 C674X_0: GEL Output: ----- C674X_0: GEL Output: DEV_INFO_24 = 0x0702100A C674X_0: GEL Output: DEV_INFO_25 = 0x08024F5B C674X_0: GEL Output: DEV_INFO_06 = 0x00000080 C674X_0: GEL Output: DEV_INFO_26 = 0x47B20000 C674X_0: GEL Output: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | BOOTROM Info | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: ROM ID: d800k003 C674X_0: GEL Output: Silicon Revision 2.0 C674X_0: GEL Output: Boot Mode: SPI0 Flash C674X_0: GEL Output: ROM Status Code: 0x000000F5 Description:C674X_0: GEL Output: Error code not recognized C674X_0: GEL Output: Program Counter (PC) = 0xC1FB22C4 C674X_0: GEL Output: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | Clock Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: C674X_0: GEL Output: PLLs configured to utilize crystal. C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2 C674X_0: GEL Output: C674X_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based C674X_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware C674X_0: GEL Output: you should change the #define in the top of the gel file, save it, C674X_0: GEL Output: and then reload. C674X_0: GEL Output: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | PLL0 Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: C674X_0: GEL Output: PLL0_SYSCLK1 = 300 MHz C674X_0: GEL Output: PLL0_SYSCLK2 = 150 MHz C674X_0: GEL Output: PLL0_SYSCLK3 = 300 MHz C674X_0: GEL Output: PLL0_SYSCLK4 = 75 MHz C674X_0: GEL Output: PLL0_SYSCLK5 = 50 MHz C674X_0: GEL Output: PLL0_SYSCLK6 = 300 MHz C674X_0: GEL Output: PLL0_SYSCLK7 = 37 MHz C674X_0: GEL Output: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | PSC0 Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: C674X_0: GEL Output: State Decoder: C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off) C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on) C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off) C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on) C674X_0: GEL Output: >3 = Transition in progress C674X_0: GEL Output: C674X_0: GEL Output: Module 0: EDMA3CC (0) STATE = 3 C674X_0: GEL Output: Module 1: EDMA3 TC0 STATE = 3 C674X_0: GEL Output: Module 2: EDMA3 TC1 STATE = 3 C674X_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3 C674X_0: GEL Output: Module 4: SPI 0 STATE = 3 C674X_0: GEL Output: Module 5: MMC/SD 0 STATE = 3 C674X_0: GEL Output: Module 6: AINTC STATE = 3 C674X_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3 C674X_0: GEL Output: Module 9: UART 0 STATE = 3 C674X_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3 C674X_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3 C674X_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3 C674X_0: GEL Output: Module 13: PRUSS STATE = 3 C674X_0: GEL Output: Module 14: ARM STATE = 0 C674X_0: GEL Output: Module 15: DSP STATE = 3 C674X_0: GEL Output: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | PSC1 Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: C674X_0: GEL Output: State Decoder: C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off) C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on) C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off) C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on) C674X_0: GEL Output: >3 = Transition in progress C674X_0: GEL Output: C674X_0: GEL Output: Module 1: USB0 (2.0) STATE = 3 C674X_0: GEL Output: Module 2: USB1 (1.1) STATE = 3 C674X_0: GEL Output: Module 3: GPIO STATE = 3 C674X_0: GEL Output: Module 4: UHPI STATE = 3 C674X_0: GEL Output: Module 5: EMAC STATE = 3 C674X_0: GEL Output: Module 6: EMIFB (BR20) STATE = 3 C674X_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 3 C674X_0: GEL Output: Module 8: MCASP1 + FIFO STATE = 3 C674X_0: GEL Output: Module 9: MCASP2 + FIFO STATE = 3 C674X_0: GEL Output: Module 10: SPI 1 STATE = 3 C674X_0: GEL Output: Module 11: I2C 1 STATE = 3 C674X_0: GEL Output: Module 12: UART 1 STATE = 3 C674X_0: GEL Output: Module 13: UART 2 STATE = 3 C674X_0: GEL Output: Module 16: LCDC STATE = 3 C674X_0: GEL Output: Module 17: eHRPWM (all) STATE = 3 C674X_0: GEL Output: Module 20: eCAP (all) STATE = 3 C674X_0: GEL Output: Module 21: eQEP 0/1 STATE = 3 C674X_0: GEL Output: Module 24: SCR8 (Br15) STATE = 3 C674X_0: GEL Output: Module 25: SCR7 (Br12) STATE = 3 C674X_0: GEL Output: Module 26: SCR12 (Br18) STATE = 3 C674X_0: GEL Output: Module 31: L3 RAM (Br13) STATE = 3
Rev 2.1 before load: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | Device Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: DEV_INFO_00 = 0x9B7DF02F C674X_0: GEL Output: DEV_INFO_01 = 0x00000000 C674X_0: GEL Output: DEV_INFO_02 = 0x0000F375 C674X_0: GEL Output: DEV_INFO_03 = 0x00000003 C674X_0: GEL Output: DEV_INFO_04 = 0x00000000 C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0 C674X_0: GEL Output: DEV_INFO_06 = 0x00000080 C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 8-0-154599-22-15-30 C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 1,0,0,11518 C674X_0: GEL Output: ----- C674X_0: GEL Output: DEV_INFO_17 = 0x00030003 C674X_0: GEL Output: DEV_INFO_18 = 0x00000000 C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: C674X_0: GEL Output: ----- C674X_0: GEL Output: DEV_INFO_20 = 0x30303864 C674X_0: GEL Output: DEV_INFO_21 = 0x3530306B C674X_0: GEL Output: DEV_INFO_22 = 0x00000000 C674X_0: GEL Output: DEV_INFO_23 = 0x00000000 C674X_0: GEL Output: ----- C674X_0: GEL Output: DEV_INFO_24 = 0x1601E00F C674X_0: GEL Output: DEV_INFO_25 = 0x08025BE7 C674X_0: GEL Output: DEV_INFO_06 = 0x00000080 C674X_0: GEL Output: DEV_INFO_26 = 0x59FC0001 C674X_0: GEL Output: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | BOOTROM Info | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: ROM ID: d800k005 C674X_0: GEL Output: Silicon Revision UNKNOWN C674X_0: GEL Output: Boot Mode: SPI0 Flash C674X_0: GEL Output: ROM Status Code: 0x00000000 Description:C674X_0: GEL Output: No error C674X_0: GEL Output: Program Counter (PC) = 0xC1FB2CD4 C674X_0: GEL Output: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | Clock Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: C674X_0: GEL Output: PLLs configured to utilize crystal. C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2 C674X_0: GEL Output: C674X_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based C674X_0: GEL Output: off OSCIN = 24 MHz. If that value does not match your hardware C674X_0: GEL Output: you should change the #define in the top of the gel file, save it, C674X_0: GEL Output: and then reload. C674X_0: GEL Output: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | PLL0 Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: C674X_0: GEL Output: PLL0_SYSCLK1 = 300 MHz C674X_0: GEL Output: PLL0_SYSCLK2 = 150 MHz C674X_0: GEL Output: PLL0_SYSCLK3 = 300 MHz C674X_0: GEL Output: PLL0_SYSCLK4 = 75 MHz C674X_0: GEL Output: PLL0_SYSCLK5 = 50 MHz C674X_0: GEL Output: PLL0_SYSCLK6 = 300 MHz C674X_0: GEL Output: PLL0_SYSCLK7 = 37 MHz C674X_0: GEL Output: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | PSC0 Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: C674X_0: GEL Output: State Decoder: C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off) C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on) C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off) C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on) C674X_0: GEL Output: >3 = Transition in progress C674X_0: GEL Output: C674X_0: GEL Output: Module 0: EDMA3CC (0) STATE = 3 C674X_0: GEL Output: Module 1: EDMA3 TC0 STATE = 3 C674X_0: GEL Output: Module 2: EDMA3 TC1 STATE = 3 C674X_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3 C674X_0: GEL Output: Module 4: SPI 0 STATE = 3 C674X_0: GEL Output: Module 5: MMC/SD 0 STATE = 3 C674X_0: GEL Output: Module 6: AINTC STATE = 3 C674X_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3 C674X_0: GEL Output: Module 9: UART 0 STATE = 3 C674X_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3 C674X_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3 C674X_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3 C674X_0: GEL Output: Module 13: PRUSS STATE = 3 C674X_0: GEL Output: Module 14: ARM STATE = 0 C674X_0: GEL Output: Module 15: DSP STATE = 3 C674X_0: GEL Output: C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: | PSC1 Information | C674X_0: GEL Output: --------------------------------------------- C674X_0: GEL Output: C674X_0: GEL Output: State Decoder: C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off) C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on) C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off) C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on) C674X_0: GEL Output: >3 = Transition in progress C674X_0: GEL Output: C674X_0: GEL Output: Module 1: USB0 (2.0) STATE = 3 C674X_0: GEL Output: Module 2: USB1 (1.1) STATE = 3 C674X_0: GEL Output: Module 3: GPIO STATE = 3 C674X_0: GEL Output: Module 4: UHPI STATE = 3 C674X_0: GEL Output: Module 5: EMAC STATE = 3 C674X_0: GEL Output: Module 6: EMIFB (BR20) STATE = 3 C674X_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 3 C674X_0: GEL Output: Module 8: MCASP1 + FIFO STATE = 3 C674X_0: GEL Output: Module 9: MCASP2 + FIFO STATE = 3 C674X_0: GEL Output: Module 10: SPI 1 STATE = 3 C674X_0: GEL Output: Module 11: I2C 1 STATE = 3 C674X_0: GEL Output: Module 12: UART 1 STATE = 3 C674X_0: GEL Output: Module 13: UART 2 STATE = 3 C674X_0: GEL Output: Module 16: LCDC STATE = 3 C674X_0: GEL Output: Module 17: eHRPWM (all) STATE = 3 C674X_0: GEL Output: Module 20: eCAP (all) STATE = 3 C674X_0: GEL Output: Module 21: eQEP 0/1 STATE = 3 C674X_0: GEL Output: Module 24: SCR8 (Br15) STATE = 3 C674X_0: GEL Output: Module 25: SCR7 (Br12) STATE = 3 C674X_0: GEL Output: Module 26: SCR12 (Br18) STATE = 3 C674X_0: GEL Output: Module 31: L3 RAM (Br13) STATE = 3 after load: no difference except program counter after run: only differences: ROM Status Code: 0x000000FF Description:C674X_0: GEL Output: Error code not recognized No change after assertion except pgm counter.
