What's the longest time DSP/BIOS 5.41 disables interrupts on a C55x

Brad Caldwell

Hi,

For a C55xx running DSP/BIOS 5.41, what's the longest period of time BIOS will disable interrupts. The assumption here is that BIOS disables interrupts for certain critical sections. We're trying to quantify worst case interrupt latency for a particular interrupt where we're not using the dispatcher.

Thanks

over 12 years ago

0 MarkGrosen over 12 years ago

TI__Expert 4125 points

From the benchmarks in the product:

http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/dspbios/5_41_13_42/exports/docs/packages/ti/bios/benchmarks/html/benchmarkc55large.html

For C55, interrupt latency is 139 cycles.

Mark

0 Brad Caldwell over 12 years ago in reply to MarkGrosen

TI__Genius 12595 points

Thanks Mark,

I saw that benchmark but I wasn't for sure what all was included in the number. Just to make sure, this number applies when we're not using the dispatcher, correct?

Thanks

0 MarkGrosen over 12 years ago in reply to Brad Caldwell

TI__Expert 4125 points

This metric represents the maximum duration of interrupts being disabled by the kernel, so it applies to any kind of interrupt - dispatcher or non-dispatcher.

Mark

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What's the longest time DSP/BIOS 5.41 disables interrupts on a C55x