Tiled Memory Region

What I don't get is why it needs to be separate from the SR2 frame buffer region.

 - Tiler memory is managed by Tiler IP and cannot be combined with regular memory. Different initiators will access the tiled address space (a virtual address space).The tiler IP converts into physical address .The way the pixels are stored in physical memory is different which ensures 2D accesses fall into a same DDR page making DDR b/w consumption efficient for 2D access. It is not possible to write to tiler virtual address space and read from the tiled physical memory directly as it will result in reading junk data.

My understanding is that the TILER only comes into play when a DMA is being performed by the HDVPSS VPDMA, and that all other modules just see it as normal memory (except the video may be tiled because the HDVPSS saw the tiled version when reading/writing the frames).

- This is not correct.

"If the tiler usage is disabled in the McFW, the memory allocator uses this region as extension of frame buffer region."

Where is this controlled so I can verify that we are seeing a larger frame buffer region?

  - In you usecase you can invoke SystemTiler_disableAllocator() to disable tiler memory so that it can be used as regular memory. You can refer /dvr_rdk/mcfw/src_linux/mcfw_api/usecases/multich_vdec_vdis.c for example usage.

 - You can verify it by invoking Vsys_printDetailedStatistics() API which prints free space for different heaps.