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Sitara: NAND Boot Size

Charlie Sweet
Prodigy 140 points

Other Parts Discussed in Thread: AM3517

Hi,

How do we initialize processor to identify the correct NAND size (In GPMC_Config1, we are seeing 16 bit NAND reported (bits 12 and 13) but have 8 bit NAND attached).

We are trying to identify how those bits get set.  What are the processor input pins that need to be set at boot to set bootdevicesize for 8 bits?

In the TRM, we find a reference to the BOOT_DEVICE_SIZE (bootdevicesize input pin) in section 9.1.3.3.2 but we can't find the corresponding pin number and are not sure how the BOOT_DEVICE_SIZE is configured.


Charlie/Chris

  • 0
    TI__Guru**** 393215 points
    Hi Charlie,
     
    Could you please tell us what processor you are talking about?
  • 0 in reply to Biser Gatchev-XID
    Prodigy 140 points

    Hi Biser,

    Sorry!  AM3517 ZCN package.

    tnx,

    Charlie/

  • 0 in reply to Charlie Sweet
    TI__Guru**** 393215 points
    Hi Charlie,
     
    Bus width is determined by reading the NAND parameters. This is described in AM35X TRM, Section 24.4.7.4.1 Initialization and NAND Detection.
  • 0 in reply to Biser Gatchev-XID
    Prodigy 140 points

    Hi Biser,

    I found TRM reference and checked bus width at beginning of  X-loader initialization and ID of DCh indicates 8 bit NAND (correct). 

    However, in U-Boot, readback of register config1 (0x1800 ) indicates 16 bit NAND.  How is this register getting reconfigured by either part of X-loader or U-Boot? 

    Here is the debug port output:

    Texas Instruments X-Loader 1.51 (Nov 21 2012 - 15:05:37)
    (CAT) MFR=002c ID=00dc  

    ** ID=00dc implies NAND:  (CAT) NAND: config1=0800 or at least 4Gb 8 bit wide NAND **
    Booting from nand . . .
    Starting OS Bootloader...

    U-Boot 2010.06-svn33 (Nov 26 2012 - 14:01:04)

    OMAP34xx/35xx-GP ES1.0, CPU-OPP2 L3-165MHz
    AM3517EVM Board + LPDDR/NAND
    I2C:   ready
    DRAM:  256 MiB
    NAND:  (CAT) NAND: config1=1800
    (CAT) N/AND:         1000
    (CAT) NAND: .... assuming 8 bit
    HW ECC [Kernel/FS layout] selected

    AM3517 Silicon Revision is 1.1 (A marking).

    Could there be an issue with ECC as well?

    Your feedback greatly appreciated.

    Charlie/Chris

  • 0 in reply to Charlie Sweet
    TI__Genius 15510 points

    Either x-loader or u-boot programs the GPMC registers. The settings used for the registers are in mem.h. Depending on your u-boot source, it should be in arch/arm/include/asm/arch-omap3. You can find the GPMC register values in there.

    Steve K.

  • 0 in reply to Steve Kipisz
    Expert 2060 points

    Hi charlie:

    mem.h -----> for all gpmc register values added

    mem.c ------> which chip select the nand flash is connected

    for nand size properly displaying;

    you should register in nand_ids.c file, with device id and manufacture id;

    Regards,

    santosh vastrad