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HyperLink as IPC transport

Greetings,

Is there any support or working examples of using HyperLink as a transport for IPC?  I saw another thread from about a year or two ago that said it was on the roadmap but haven't found anything else.  Using c667x, Bios 6.33.6, CCSv5.2.1; noob to all.

The prior thread was http://e2e.ti.com/support/embedded/bios/f/355/p/67395/374090.aspx#374090.

Thanks   - Ken

  • As far as I know, MessageQ transport layers that were already implemented are shared memory, Navigator and SRIO.

    There is no HyperLink implementation.  However, one can develop an implementation.

    If two devices are connected with Hyperlink, then device A can access Device B shared memory (or any other memory) like it is its own memory. Thus it should not be very difficult to modify the shared memory drivers of the messageQ to work with HyperLink. Of course address translation must be used, and HyperLink interrupt mechanism must replace the Notify interrupt that exist now, but it can be done.

    Ran

  • Thanks Ran.  It just strikes me as uncharacteristic that ready support for this is not built into the OS/IDE/libraries package, and that there doesn’t seem to be cookbook directions on how to use it as such.

    IPCs are described as “inter-processOR” communications, do they really mean inter-core?  The literature seems to treat them that way.  When I think interprocessor, I’m thinking between separate physical devices.

    HyperLink seems the natural way for processes on different chips to intercommunicate.  Is there another preferred way to use this link instead of via IPCs?  Excuse my ignorance, like I said I’m a noob here.

    - Ken

  • Well, IPC is between cores (navigator, shared memory) and between Devices  (SRIO)

    It can be between devices using HyperLink

    of courseyou can use Ethernet,  SRIO protocol or any other peripheral to communicate between devices, but I agree with you, IPC APIs are already developed and one would like to use it.

     

    One of these days we may have HyperLink version

     

    Best regards

     

    Ran

  • Ken,

    A IPC transport extension implemented over HyperLink is not currently on the BIOS MCSDK roadmap.

    For communication between cores on the same device you can use the following transports:

    - IPC over Shared memory (provided by default with the IPC component)

    - IPC over QMSS (provided as a transport extension with the BIOS MCSDK PDK component)

    For communication between cores on different devices you can use the following transport:

    - IPC over SRIO (provided as a transport extension with the BIOS MCSDK PDK component)

    Justin

  • Thanks Justin. Unfortunately my board designers are using the SRIO for something else, and are using the HyperLink as the interconnect between two c667x's.

    Maybe I should start a new thread for this, but it does flow from the above discussion...

    What is the recommended model for software use of HyperLink between chips?  Does it just make DSP A's address space (or a part of it) become a memory-mapped extension of DSP B's, and vice versa?

    - Ken

  • Ken,

    The BIOS forum is probably not the best for that type of question, but for now I will give you a little background.

    The HyperLink module was designed with the intention of allowing two C66x DSPs to share a single bank of DDR3 memory devices. This was a board space and board cost goal for certain applications in a specific market.

    As has been the case since the very first TI DSP, our ingenious customers have found many additional applications for peripherals and features that we did not envision. That is the benefit of creating a powerful engine: other people find great ways to use powerful features. As I recall hearing, Teflon was invented for for the NASA space program and found its way into revolutionizing the kitchen pots and pans for many households (I may be showing my age by knowing this). The HyperLink is a powerful peripheral that you will be able to use for things that we did not initially expect for it.

    The easiest model to support is setting the HyperLink to give you shared access to memory on the other DSP's memory map. There are other ways that can be used, such as message passing, but that is not in our current plan, as Justin has explained.

    It should not be difficult (easy for me to say) for you to implement an IPC transport layer that uses HyperLink. When you do that, you would become very popular on the E2E forum by posting your working implementation so others can follow boldly in your footsteps. As you have questions along the way, please post those in new threads in the Keystone C66x forum.

    Regards,
    RandyP

  • Thanks Randy, Ran and Justin.  I'm calling this one answered, although sadly the answer to the initial inquiry is "No".  That's show biz.

    Cheers   - Ken