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Large delay between GPMC DMA bursts

Konstantin
Intellectual 505 points
Other Parts Discussed in Thread: DM3730

Hi!

I'm using DM3730 with FPGA (connected via GPMC).

My DMA setup:

p347_fpga_info.dma_par.data_type = OMAP_DMA_DATA_TYPE_S16;
p347_fpga_info.dma_par.src_start = fpga_mem_read_base;
p347_fpga_info.dma_par.src_amode = OMAP_DMA_AMODE_POST_INC;
p347_fpga_info.dma_par.dst_start = p347_fpga_info.dma_rd_addr;
p347_fpga_info.dma_par.dst_amode = OMAP_DMA_AMODE_POST_INC;
p347_fpga_info.dma_par.dst_ei = 1;
p347_fpga_info.dma_par.dst_fi = 1;
p347_fpga_info.dma_par.elem_count = 8*64;
p347_fpga_info.dma_par.frame_count = 1;
p347_fpga_info.dma_par.sync_mode = OMAP_DMA_SYNC_FRAME;

ret = omap_request_dma(77,"p347_fpga_read_dma",p347_fpga_dma_callback,&p347_fpga_info,&p347_fpga_info.dma_ch);
omap_set_dma_params(p347_fpga_info.dma_ch,&p347_fpga_info.dma_par);
omap_set_dma_src_burst_mode(p347_fpga_info.dma_ch,OMAP_DMA_DATA_BURST_8);
omap_set_dma_dest_burst_mode(p347_fpga_info.dma_ch,OMAP_DMA_DATA_BURST_8);

My GPMC timings:

cswrofftime = 5
csrdofftime = 23
csextradelay = 0
csontime = 0
advwrofftime = 2
advrdofftime = 4
advextradelay = 0
advontime = 1
weofftime = 5
weextradelay = 0
weontime = 3
oeofftime = 22
oeextradelay = 0
oeontime = 6
pageburstaccesstime = 2
rdaccesstime = 7
wrcycletime = 7
rdcycletime = 8
wraccesstime = 3
wrdataonadmuxbus = 2
cycle2cycledelay = 1
cycle2cyclesamecsen = 0
cycle2cyclediffcsen = 1
busturnaround = 1

And my problem:

When DM3730 reads data from FPGA, an unpredictable delay between bursts appears. 

Please look at photo: why delays are so large? Why they are different? Every burst is correct.

Yellow line is GPMC_CLK.

  • 0
    Guru 31670 points

    Is it because of the OMAP_DMA_SYNC_FRAME parameter? Can you share a snapshot of the interface schematic between the DM3730 and FPGA? Do you have a FIFO inside the FPGA, and what is the depth of the FIFO if available?

  • 0 in reply to Renjith Thomas
    Intellectual 505 points

    > Is it because of the OMAP_DMA_SYNC_FRAME parameter?

    I don't think so... Frame size = 64 bursts, so SYNC_FRAME should not affect the delay between bursts.

    > Can you share a snapshot of the interface schematic between the DM3730 and FPGA?

    FPGA connected right to the GPMC lines, without any resistors or integrated circuits. But there is Ethernet and NAND connected to GPMC too... We are using TDM3730 with Blizzard board from Technexion ( http://www.technexion.com/index.php/support/download-center/arm-cpu-modules/tdm-3730 ).

    > Do you have a FIFO inside the FPGA, and what is the depth of the FIFO if available?

    Yes, we have a FIFO, size = 64*8*2 bytes (exactly 64 bursts * 8 words in burst * 2bytes in word)

    ...and we are not using WAIT pin.

  • 0 in reply to Konstantin
    TI__Guru*** 125430 points

    Are the other devices on the gpmc asynchronous or synchronous?  If they are asynchronous then your scope would not trigger since there would be no clock. Perhaps the gaps are simply transfers to the other chip selects. 

  • 0 in reply to Brad Griffis
    Intellectual 505 points

    NAND is asynchronous. Now we have checked CS pins of other devices, and they are not active.

    I guess we can get around this problem by using maximum burst size, but i'm not sure this is the right decision...

  • 0
    Guru 31670 points

    Konstantin

    Can you try with OMAP_DMA_SYNC_BLOCK instead of OMAP_DMA_SYNC_FRAME. Basically it will raise and interrupt/event when each and every frame is completed. 

  • 0 in reply to Renjith Thomas
    Intellectual 505 points

    Initially, we did a frame on one element and OMAP_DMA_SYNC_BLOCK after 64 frames. And the delay time was little more than now (~10%).

    Now we have one big frame.

    UPDATE: OMAP_DMA_SYNC_FRAME to OMAP_DMA_SYNC_BLOCK change had no effect on delays between bursts for one big frame.

  • 0 in reply to Brad Griffis
    Prodigy 10 points

    Hi Brad,

         I'm just begin to use the 8168 platform. Now I want to use the GPMC to control the NAND flash, I want to move the data from the NAND flash to the DDR using DMA mode, but I don't konw how to config the register, especially the order of the configration of the GPMC register. And when to config the GPMC register, when to config the EDMA register, I find that the dma event of GPMC is channel 52

     thanks a lot!