I am working on porting MIPI DSI LCD panel on a custom board with OMAP3715. I am facing problems in clock settings.
From the LCD datasheet, i configure the PCLK as 27MHz., 24BPP, sys_clk=26MHZ, 2 data lane:
clock lane = 27*24/4 = 162MHz
0.75< 26/(RegN + 1)<2.1 --------> REGN=12
648=2*REGM*26/12+1 ----------->REGM=162
dsi1_pll_fclk = 648/6 = 108 = dsi2_pll_fclk ---------->REGM3=REGM4=5
TxByteClkHS = 648/16= 40.5MHz
Now , i have the proble, how can i calculate DSIFCLK, if DSIFCLK = Clock lan = 162MHZ
how can i calculate VP_PCLK, if it must =27MHZ
how can i make the R=TxByteClkHS/VP_PCLK=2/3.
