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AM3874 DDR3 RCD value

Michi Yama
Guru 10030 points


Hi,

Our customer says tRCD value in SDRTIM1 register  does not work correctly.

Customer says, real clock cycle is is added one cycle to the value in register. See the below.

register value   ------  real clock cycle

5                        ------->   6

6                       -------->  6

7                       ----------> 8

8                       ----------> 8

9                      ----------> 10

Also the below is customer's register setting.

RCD=6
R;0x4c000000|40443403 00000004 69c012b2 00000000
R;0x4c000010|10000618 00000618 0aaae523 0aaae523
R;0x4c000020|202f7fda 202f7fda 501f82bf 501f82bf
R;0x4c000030|00000000 00000000 00000000 00000000
RCD=7
R;0x4c000000|40443403 00000004 69c012b2 00000000
R;0x4c000010|10000618 00000618 0acae523 0acae523
R;0x4c000020|202f7fda 202f7fda 501f82bf 501f82bf
R;0x4c000030|00000000 00000000 00000000 00000000

Then, the below picture is the waveform that our customer measured.

As you see, clock cycle is 8 when RCD=7 setting.

If you have some information for this symptom, please let me know.

Best regards,

Michi

  • 0
    TI__Guru**** 393215 points
    Hi Michi,
     
    From AM387X TRM, Table 7-40:
     
    24-21      T_RCD          4h              Specifies the mimimum number of DDR[X]_CLK cycles from an activate command to read or write
                                                               command, minus 1. Corresponds to tRCD AC timing parameter in the DDR2/3/LPDDR1 data sheet.
                                                               Calculated by T_RP=(tRCD/DDR[X]_CLK period)-1.

  • 0 in reply to Biser Gatchev-XID
    Guru 10030 points

    Dear Biser-san,

    Thank you for your advise.

    I would like to confirm one thing. According to the Table 7-41 on the TRM,  it is written that "Calculated by T_RP=(tRCD/DDR[X]_CLK period)-1." , as you said.

    But according to the Table 7- 21, it is written that "Formula is (tRCDx fDDR[X]_CLK)-1" . I think "T_RP=(tRCD/DDR[X]_CLK period)-1" of Table7-41 is wrong.

    Is my thought right?

    Please let me know.

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    Guru 10030 points

    Dear Biser-san,

    In my previous question,  I found my mistake.

    I said "T_RP=(tRCD/DDR[X]_CLK period)-1" of Table7-41 is wrong".

    But  I think the correct formula is "T_RCD=(tRCD / fDDR[X]_CLK)-1". In other words,

    Table 7-41 : T_RP -----> T_RCD

    Table7-21: tRCD x fDDR[X]_CKL ------> tRCD/fDDR[X]_CLK 

    Is my understand righta?

     

    Best regards,

    Michi

  • 0 in reply to Michi Yama
    TI__Guru**** 393215 points
    Hi Michi,
     
    Yes, this is correct.
  • 0 in reply to Biser Gatchev-XID
    Guru 10030 points

    Dear Biser-san,

    Thank you for your support.

    I would like to confirm one more thing.

    I understood the value of register setting is real clock minus 1 as you mentioned.

    I don't know one thing. Please see  the following.

    register value   ------  real clock cycle

    5                        ------->   6

    6                       -------->  6

    7                       ----------> 8

    8                       ----------> 8

    9                      ----------> 10

    As you see, the vaule of register "6" and "8" are the same as real clock.

    Why? I must answer this point to the customer . Please advise me.

    Best regards,

    Michi

     

  • 0 in reply to Michi Yama
    TI__Guru**** 393215 points
    Hi Michi,
     
    I don't have an answer for this.