SRIO PLL doesn't lock with high MPY value

After agreement with the initiator of this thread, please find here additional information and questions.

The desired data rate is 3.125 Gbps when trying to get the SRIO bus to work between TMS320C6678 and an FPGA on the same circuit board. The aim is to run each of the four ports at 3.125 Gbps.

"I built the SRIOLoopbackDioIsr example project from pdk_C6678_1_0_0_15 with CCS and loaded into core #4 of the TMS320C6678. All the other cores were loaded with programs using our own operating system. I did a small change in the file loopbackDioIsr.c:

/* Defines the core number responsible for system initialization. */
// #define CORE_SYS_INIT               0
#define CORE_SYS_INIT               3     // SRIO code loaded in DSP4

and some address changes in the file linker.cmd (to avoid affecting other cores) that resulted in this memory configuration:

  name                             origin           length        used          unused     attr           fill
  ----------------------           --------           ---------         --------         --------         ----           --------
  MSMCSRAM              0c010000   00200000  001025fc  000fda04  RW X
  L2SRAM                      13804100   00070000  00030074  0003ff8c    RW X
  DDR3                           80000000   20000000  00000000  20000000  RWIX

The original example that uses the digital loopback feature passed all tests, but the debug counter srioDioLsuErrTransferErr was incremented every time the interrupt routine myDioTxCompletionIsr was executed. A behaviour that was repeated in all the tests I did. Do you know why this happens?

Next I tried to include the SERDES units in the loop by doing some changes in the file device_srio_loopback.c:

    CSL_SRIO_SetNormalMode(hSrio, 0);
    CSL_SRIO_SetNormalMode(hSrio, 1);
    CSL_SRIO_SetNormalMode(hSrio, 2);
    CSL_SRIO_SetNormalMode(hSrio, 3);

    /* Assuming the link rate is 3125; program the PLL accordingly. */
    CSL_BootCfgSetSRIOSERDESConfigPLL (0x251);  // 10x, PS935E has ref_clock 156.25 MHz

    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x01C40495);  // SERDES loopback half rate
    CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x01C40495);
    CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x01C40495);
    CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x01C40495);

    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00780795);  // SERDES loopback half rate
    CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00780795);
    CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00780795);
    CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00780795);

This should give a data rate of 3.125 Gbps.The test passed the first call of the function dioSocketsWithISR (DIO Write Operation), but got stuck during the second call (DIO Read Operation), waiting for srioLsuIsrServiced. For some reason the counter TSCL was never incremented, so the timeout didn't work.

Then I changed the rate bits in the config registers to quarter rate (0b10) giving a data rate of 1.5625 Gbps. The result was that about 50% of the attempts the test passed completely and at the other attempts it got stuck during DIO Read Operation.

Finally I changed the MPY factor in the PLL config register to 5x and still quarter rate, giving a data rate of 0.78125 Gbps. Then the test passed completely every time.

Can you see any problem with the way the clock reference is connected to the Dsp, or is there any register setting that can help us obtain the desired data rate of 3.125 Gbps? " 

Please note it's a typo in the schmetic, it should be C6678, not C6672.

Gunnar,

The PLL VCO is the Ref. Clock * MPY. The PLL VCO should be within the nominal range 1.5625 - 3.126 GHz so that confuses me why a MPY with 5 does not work when using a Ref. Clock of 156.25 MHz.

Please explain how you see that the PLL is locked and then becomes unlocked. 

Frederick,

A line rate of .78125 is not even acceptable. You should be only using 5, 3.125, 2.5, or 1.25 Gbps line rates. Can you explain these tests that pass/fail in your different testing environments?

Make sure to follow this table in the SRIO UG (updated in December 2012)

The 156.25 MHz ref. clock with MPY 5 is not even valid. Can you raise your ref clk?

Elush Shirazpour

Gunnar

I have attached a SERDES GEL file. A GEL file is a debugging tool used by the CCS to help the user catch any bugs. I assume you have the CCS v5.

To use the GEL file:

1. Enter into CCS Debug Mode (should be in the top right of CCS next to CCS Edit) and you have ran your program or paused your program.
2. Select Tools->GEL files
3. A GEL Files tab should open up
4. Right click in an entry under Script/Status table and select "Load Gel..."
5. Select the GEL file I have given you and wait for its status under the Script/Status table to turn to "Success".
6. Select Scripts and see all the different tests provided.

 After you have initialized the SERDES and right before you run the tests, run the SERDES Status for SRIO and SERDES SRIO Config to see if the values you have placed are what you expected. 

Elush Shirazpour

4604.Nyquist_SystemDebug_v0.5.gel

Hi Elush,

when we use 5x PLL and Full rate with our 156.25 MHz clock (which is a not recommended mode but the only one that works for us) bit 0 of the register SRIO_SERDES_STS (0x02620154) stays at 1 all the time, but when we change to 10x PLL and Half rate (which is a recommended mode), bit 0 sometimes reads 0.

We are still using silicon revision 1.0 of the TMS320C6678. Do you think this problem will be solved with rev. 2.0 (which we will get shortly)? There is a lot of SRIO erratas for rev. 1.0.

Thanks, Gunnar

I noticed that on the development board, TMDXEVM6678L, the SRIO clock is coming from a clock generator called TI_CDCE62005RGZT (312.5 MHz), while we are using a generator called EG-2121 (156.25 MHz) on our board. Do you think this difference can explain why the SRIO PLL doesn't lock with 10x PLL?

Gunnar

That is a big possibility.

Elush