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Does TSCL,H requirement B side register to read?

Hi,

I want to use TSCL, TSCH timer in assembler. I encounter an error which says it expects B side register. I do not see that statement in the user manual. Is that ture?

My DSP software: CCS v5.1. 6678 DSP.

 

Thanks,

 

The following code is copied from page 64,

TMS320C66x DSP CPU and Instruction Set

Literature Number: SPRUGH7

November 2010

 

..........

MVC TSCL,A0                   ; A0 = 0

MVC TSCH,A1                  ; A1 = 1

.................................

"../asm_printf.asm", ERROR!   at line 9: [E0004] B side register required for destination register A0

2 Assembly Errors, No Assembly Warnings

MVC TSCL,A0 ; A0 = 0

"../asm_printf.asm", ERROR! at line 10: [E0004] B side register required for destination register A1

MVC TSCH,A1 ; A1 = 1

  • A further development of the last problem is here. Although I can change the A0 register to B0, an error message appears now. It says it cannot read REP control register. Please see the picture. What causes the problem and what is the solution?

     

    Thanks,

  • Robert,

    Embarrassingly, the examples in the CPU & Instruction Set Reference Guide use A0 and A1 exactly as you tried to do. But the error message is clear and correct.

    You can read the instruction description for the MVC instruction in that Reference Guide to see that it only executes on the S2 functional unit. This B-side requirement applies to the destination register for any instruction that executes on any .X2 functional unit: .S2, .D2, .L2, .M2.

    If you replace your MVC A0, TSCL with MVC B0, TSCL do you also get the REP error?

    Regards,
    RandyP

  • Thanks for the confirmation.

    That error is still there. Whenever the ControlRegisters window opens, there will a Trouble Reading error pops up for each instruction step. It is not only for TSCL read/write.

  • That is a tough one. I have never had this issue, so I cannot make any suggestions. Perhaps someone else will see this and offer some better advice.

    It goes away when you are not displaying the Core Registers windows, is that correct?

    Are you in User mode? The CPU & Instruction Set Reference Guide says this is one of many registers that is not accessible in User mode, but others from that list are not giving you trouble.

    Regards,
    RandyP

  • I only run a simple C/asm mix program. I do not use the CPU previlege level at all.

    It goes away when you are not displaying the Core Registers windows, is that correct?

    Yes.

    Are you in User mode? The CPU & Instruction Set Reference Guide says this is one of many registers that is not accessible in User mode, but others from that list are not giving you trouble.

    I do not change mode, but it is clear that after I add MVC instruction this happens.

  • Robert,

    This is very unusual, and I have used the TSCL register many times.

    If you close CCS, power cycle your board, re-open CCS, change the code to use only B-side registers with the MVC instructions, will you still get this?

    If not, I can only think to recommend making sure your CCS and emulation drivers are all updated to the latest.

    Regards,
    RandyP

  • Excuse me. I do not mean in emulator mode. I use it in TI simulator (software simulator).

  • And I just realized this is the C67x Single Core DSP Forum, while the C6678 questions should be in the Keystone C66x Forum. We will have this thread moved there for you in case they know anything new.

    It is probably just a simulator mistake. If you want to pursue it after any responses in the Keystone forum, you will want to post a simulator question on the Code Composer Forum. We have a lot of people working the forums, and they all concentrate on their own areas of expertise. That can make it hard for you to figure out the best place, and we apologize for that. Tough tradeoffs had to be made.

    Regards,
    RandyP