Hello,
I plan to use the C6748 DSP and to interface it with an FPGA using the UPP bus. Reading the UPP user guide(sprugj5b), I understand that all the data transfer have to be multiple of 64bytes (it depends on TXSIZEA/B and RDSIZEQ/I configuration which is a multiple of 64). Am I right?
If we have discontinuous transfer of samples from the FPGA to the DSP (not systematically a multiple of 64), it means that we need to pad the last samples to complete the reception?
Laurent.