I use am335x EVM board for test and find the default value of conf_lcd_data0~conf_lcd_data15 is always 0x2f, whether or not i set conf_lcd_data0~conf_lcd_data3 to value 0x08 ( this config 4 pins for LCD_DATA0~LCD_DATA3), it seems no influence to the color of display , however other pins (from LCD_DATA4~LCDDATA23), it must be set the conf_lcd_datax register to the right value.
It meens set register conf_lcd_data0~data3 has no effect to LCD_DATA0~LCD_DATA3 pin. With the default value 0x2f ,it works well!? however, according to the spec, 0x2f meens config these pins to GPIO !?
I can't explain this, could u tell me why?
And, it's strange that if i set conf_lcd_data0~data3, my application run on QNX platform is not stable, the app always crash with inexplainable reason, it seems access address 0 or not mapped address, if i comment out this 4 sentence , it's ok, my application run stable.
The function i use to init pinmux for LCD below:
static void init_lcd_pin_mux(void)
{
//out32(conf_lcd_data0 , MODE(0) | PULLUDDIS); // LCD_DATA0/GPMC_A0//EHRPWM2A//PR1_PRU1_PRU_R30_0/PR1_PRU1_PRU_R31_0/GPIO2_6
//out32(conf_lcd_data1 , MODE(0) | PULLUDDIS); //
//out32(conf_lcd_data2 , MODE(0) | PULLUDDIS); //
//out32(conf_lcd_data3 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data4 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data5 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data6 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data7 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data8 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data9 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data10 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data11 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data12 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data13 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data14 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_data15 , MODE(0) | PULLUDDIS); //
out32(conf_lcd_vsync , MODE(0)); // //LCD_VSYNC/GPMC_A8//PR1_EDIO_DATA_IN2/PR1_EDIO_DATA_OUT2/PR1_PRU1_PRU_R30_8/PR1_PRU1_PRU_R31_8/GPIO2_22
out32(conf_lcd_hsync , MODE(0)); // //LCD_HSYNC/GPMC_A9//PR1_EDIO_DATA_IN3/PR1_EDIO_DATA_OUT3/PR1_PRU1_PRU_R30_9/PR1_PRU1_PRU_R31_9/GPIO2_23
out32(conf_lcd_pclk , MODE(0)); // //LCD_PCLK/GPMC_A10//PR1_EDIO_DATA_IN4/PR1_EDIO_DATA_OUT4/PR1_PRU1_PRU_R30_10/PR1_PRU1_PRU_R31_10/GPIO2_24
out32(conf_lcd_ac_bias_en , MODE(0)); // //LCD_AC_BIAS_EN/GPMC_A11//PR1_EDIO_DATA_IN5/PR1_EDIO_DATA_OUT5/PR1_PRU1_PRU_R30_11/PR1_PRU1_PRU_R31_11/GPIO2_25
// out32(conf_ecap0_in_pwm0_out, MODE(0); // //ECAP0_IN_PWM0_OUT/UART3_TXD/SPI1_CS1/PR1_ECAP0_ECAP_CAPIN_APWM_O/SPI1_SCLK/MMC0_SDWP/XDMA_EVENT_INTR2/GPIO0_7
// out32(conf_ecap0_in_pwm0_out, MODE(7)); //ECAP0_IN_PWM0_OUT/UART3_TXD/SPI1_CS1/PR1_ECAP0_ECAP_CAPIN_APWM_O/SPI1_SCLK/MMC0_SDWP/XDMA_EVENT_INTR2/GPIO0_7
}