Other Parts Discussed in Thread: TPS386596
I am running with the following:
C6748
BIOS 5.41.10.36
NDK 2.20.3.24
CCS 4.2
AIS NOR boot (16 bit)
The firmware boots from NOR and comes up just fine on a power cycle. We are trying to do a software controlled reset. We have a GPIO line tied to a power monitor reset device which is active low. The device drives the Reset line of the CPU low for 50 msec when this GPIO activated.
The GPIO is initialized before BIOS runs:
// Disable reset output
GPIO_setOutput(dsp_reset_out.bank, dsp_reset_out.pin_num, 1); // inactive
GPIO_setDir(dsp_reset_out.bank, dsp_reset_out.pin_num, GPIO_OUTPUT);
The code to activate the warm reset is as follows:
GPIO_setDir(dsp_reset_out.bank, dsp_reset_out.pin_num, GPIO_OUTPUT);
GPIO_setOutput(dsp_reset_out.bank, dsp_reset_out.pin_num, 0); // active
The soft reboot worked, but then following minor code changes does not. It seems sensitive to the order of the two lines above. The bootloader fails and stops at address 0x00712144 IDLE instruction. I tried disabling interrupts before resetting, but the reboot still fails (although it succeeded when I single stepped through these 3 lines):
// Reboot
_disable_interrupts();
GPIO_setDir(dsp_reset_out.bank, dsp_reset_out.pin_num, GPIO_OUTPUT);
GPIO_setOutput(dsp_reset_out.bank, dsp_reset_out.pin_num, 0); // active
I believe the NOR is fine since a power cycle reboot works fine. It is an AIS NOR boot. CE2CFG = 0x3FFFFFFD after a successfull boot. The top of the NOR contains:
21 00 00 00 54 49 50 41 0D 59 53 58 00 00 02 00 01 00 18 00 05 02 00 00 0D 59
53 58 04 00 05 00 21 45 00 00 10 45 11 29 06 00 00 00 0E 03 00 00 00 00 00 00
0D 59 53 58 05 00 05 00 FD FF FF 3F 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00
Is there something that needs to be done to prepare for a warm reset?
I downloaded the OMAPLx_debug.gel and ran the diagnostics after a failed reboot:
C674X_0: GEL Output: | Device Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
C674X_0: GEL Output: DEV_INFO_02 = 0x00000002
C674X_0: GEL Output: DEV_INFO_03 = 0x00000002
C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-5641834-10-36-13
C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 2,0,0,3762
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
C674X_0: GEL Output: DEV_INFO_21 = 0x3630306B
C674X_0: GEL Output:
---------------------------------------------
C674X_0: GEL Output: | Device Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
C674X_0: GEL Output: DEV_INFO_02 = 0x00000002
C674X_0: GEL Output: DEV_INFO_03 = 0x00000002
C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-5641834-10-36-13
C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 2,0,0,3762
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
C674X_0: GEL Output: DEV_INFO_21 = 0x3630306B
C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_24 = 0x0A00D024
C674X_0: GEL Output: DEV_INFO_25 = 0x0056166A
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_26 = 0x1D640002
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | BOOTROM Info |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: ROM ID: d800k006
C674X_0: GEL Output: Silicon Revision 2.0
C674X_0: GEL Output: Boot Mode: NOR
C674X_0: GEL Output:
ROM Status Code: 0x00000005
Description:C674X_0: GEL Output: Peripheral Open Failed
C674X_0: GEL Output:
Program Counter (PC) = 0x00712144
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | Clock Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLLs configured to utilize crystal.
C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
C674X_0: GEL Output:
C674X_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
C674X_0: GEL Output: off OSCIN = 25 MHz. If that value does not match your hardware
C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
C674X_0: GEL Output: and then reload.
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | PLL0 Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL0_SYSCLK1 = 25 MHz
C674X_0: GEL Output: PLL0_SYSCLK2 = 12 MHz
C674X_0: GEL Output: PLL0_SYSCLK3 = 25 MHz
C674X_0: GEL Output: PLL0_SYSCLK4 = 6 MHz
C674X_0: GEL Output: PLL0_SYSCLK5 = 25 MHz
C674X_0: GEL Output: PLL0_SYSCLK6 = 25 MHz
C674X_0: GEL Output: PLL0_SYSCLK7 = 4 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | PLL1 Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL1_SYSCLK1 = 25 MHz
C674X_0: GEL Output: PLL1_SYSCLK2 = 12 MHz
C674X_0: GEL Output: PLL1_SYSCLK3 = 25 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | PSC0 Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0: EDMA3CC (0) STATE = 0
C674X_0: GEL Output: Module 1: EDMA3 TC0 STATE = 0
C674X_0: GEL Output: Module 2: EDMA3 TC1 STATE = 0
C674X_0: GEL Output: Module 3: EMIFA (BR7) STATE = 3
C674X_0: GEL Output: Module 4: SPI 0 STATE = 0
C674X_0: GEL Output: Module 5: MMC/SD 0 STATE = 0
C674X_0: GEL Output: Module 6: AINTC STATE = 3
C674X_0: GEL Output: Module 7: ARM RAM/ROM STATE = 3
C674X_0: GEL Output: Module 9: UART 0 STATE = 0
C674X_0: GEL Output: Module 10: SCR 0 (BR0/1/2/8) STATE = 3
C674X_0: GEL Output: Module 11: SCR 1 (BR4) STATE = 3
C674X_0: GEL Output: Module 12: SCR 2 (BR3/5/6) STATE = 3
C674X_0: GEL Output: Module 13: PRUSS STATE = 0
C674X_0: GEL Output: Module 14: ARM STATE = 0
C674X_0: GEL Output: Module 15: DSP STATE = 3
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: | PSC1 Information |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0: EDMA3CC (1) STATE = 0
C674X_0: GEL Output: Module 1: USB0 (2.0) STATE = 0
C674X_0: GEL Output: Module 2: USB1 (1.1) STATE = 0
C674X_0: GEL Output: Module 3: GPIO STATE = 0
C674X_0: GEL Output: Module 4: UHPI STATE = 0
C674X_0: GEL Output: Module 5: EMAC STATE = 0
C674X_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 0
C674X_0: GEL Output: Module 7: MCASP0 + FIFO STATE = 0
C674X_0: GEL Output: Module 8: SATA STATE = 0
C674X_0: GEL Output: Module 9: VPIF STATE = 0
C674X_0: GEL Output: Module 10: SPI 1 STATE = 0
C674X_0: GEL Output: Module 11: I2C 1 STATE = 0
C674X_0: GEL Output: Module 12: UART 1 STATE = 0
C674X_0: GEL Output: Module 13: UART 2 STATE = 0
C674X_0: GEL Output: Module 14: MCBSP0 + FIFO STATE = 0
C674X_0: GEL Output: Module 15: MCBSP1 + FIFO STATE = 0
C674X_0: GEL Output: Module 16: LCDC STATE = 0
C674X_0: GEL Output: Module 17: eHRPWM (all) STATE = 0
C674X_0: GEL Output: Module 18: MMC/SD 1 STATE = 0
C674X_0: GEL Output: Module 19: UPP STATE = 0
C674X_0: GEL Output: Module 20: eCAP (all) STATE = 0
C674X_0: GEL Output: Module 21: EDMA3 TC2 STATE = 0
C674X_0: GEL Output: Module 24: SCR-F0 Br-F0 STATE = 3
C674X_0: GEL Output: Module 25: SCR-F1 Br-F1 STATE = 3
C674X_0: GEL Output: Module 26: SCR-F2 Br-F2 STATE = 3
C674X_0: GEL Output: Module 27: SCR-F6 Br-F3 STATE = 3
C674X_0: GEL Output: Module 28: SCR-F7 Br-F4 STATE = 3
C674X_0: GEL Output: Module 29: SCR-F8 Br-F5 STATE = 3
C674X_0: GEL Output: Module 30: Br-F7 (DDR Contr) STATE = 3
C674X_0: GEL Output: Module 31: L3 RAM, SCR-F4, Br-F6 STATE = 3
C674X_0: GEL: Error loading file 'D:\Vishay\Gel\C6748_MM_SDRAM_PLL.gel': function 'OnTargetConnect()' already defined
C674X_0: Output: PLL0 init done for Core:300MHz, EMIFA:100MHz
C674X_0: Output: EMIFA Pins Configured.
C674X_0: Output: ---------------------------------------------
