c6678 hyperlink interrupt

Hi,

Please tell me more detail. are you using TI Hyperlink LLD example project for your test? if it is, you just can run DSPA first and then run DSPB later and both will have perfect synchronization after they got SERDES link up. you said you run those two DSPs at the same time after you stopped at a breakpoint for a while. did you just press the run button for those two DSPs at the same time or run DSPa first and then run DSPb second?

and how did you check the status when you didn't get interrupt from one of your DSP. did you just check your ISR on one DSP doesn't work or read hyperlink interrupt set pending registers to confirm if it was really set or not. how many times you run your code? have you tried multiple number of interrupt triggering with certain amount of delay without reset those two hyperlinks?

Hyperlink normally requires certain amount of time to establish safe physical layer training. you may try to insert some time delay on your code before triggerring interrupt.

Regards,

Albert  

Hi，

I  use the TI Hyperlink LLD example for the test, My board has two c6678 DSPs, When I test,I group the DSPA core0 and DSPB core0,  and the Run, this make the two DPS run together. The SERDES link up, because the console has output info. 

I use two ways to test the interrupt, one is interrupt packet and the other is directly writting the remote interrupt pending/set register , two ways both can generate interrupt if I have a breakpoint before generating the interrupt. If there is no breakpoint, then one DSP's interrupt pending/set register is not set, and the other is set.  I try to have a delay instead of breakpoint ,it does not work! I test many times,every time I test, I do the system reset. So I am not sure where the matter is! Please give me some advice.

Thank you!

How large amount of delay you put into your code? try very large delay (around one second) for both side.

Next thing you can try is switching SERDES configuration order. please try procedure below.

1. SERDES Tx configuration. ==> 2. SERDES Rx configuration. ==> 3. SERDES Common (PLL) configuration

and also check your "link status register" (offset 0x58) if "rx_one_id" field is high when SERDES training is done.  

Albert

Hi Albert,

I follow you advice, But  the problem still  happens. Can you give me other advice. Forgot to say, my hyperlink is configured 4*6.25Gbps. 

Best Regards

6.25 Gbps link speed should be fine.  you didn't tell me the answer for my question, if you could see correct "rx_one_id" field in link status register was up before you trigger interrupt. other things you can try is inserting assymetric (not equal) delay for each DSPs and see what's going on. have you tried long time delay (more than one second) for both side. you need to tell me your test result detail to go further step.

Albert

I am sorry , I have done what you tell me , and  no matter before or after sending interrupt packet, the "rx_one_id" field in link status register  set 1. And I have some delay from 1s to 15s before sending interrupt packet for both side, include not equal delay and equal delay , but it is same with before.

When I test the  not equal delay , I find if DSPA delay longer than DSPB, then DSPB can receive interrupt while DSPA can't., if DSPB delay longer than DSPA, then DSPA can receive interrupt while DSPB can't.

Here is my code for sending interrupt. Is there any error?

#define HYPERLINK_BASEADDR                                                          (0x21400000)
#define LOC_CONTROL                                                                       *(volatile unsigned int*)(HYPERLINK_BASEADDR + 0x4)
#define LOC_PRIORITY_VECTOR_STATUS_CLEAR                        *(volatile unsigned int*)(HYPERLINK_BASEADDR + 0xc)
#define LOC_INTSTATE                                                                       *(volatile unsigned int*)(HYPERLINK_BASEADDR + 0x10)
#define LOC_INTPENDSET                                                                 *(volatile unsigned int*)(HYPERLINK_BASEADDR + 0x14)
#define LOC_GENARATE_SOFT_INT_VALUE                                    *(volatile unsigned int*)(HYPERLINK_BASEADDR + 0x18)

#define LOC_INT_CTRL_IDX                                                                *(volatile unsigned int*)(HYPERLINK_BASEADDR + 0x60)
#define LOC_INT_CTR_VALUE                                                            *(volatile unsigned int*)(HYPERLINK_BASEADDR + 0x64)

void Hyperlink_SendIntPacket(nInfo)
{
         LOC_CONTROL &= 0x3fff; //intlocal = 0
         LOC_CONTROL |= (1 << 13)\
                                      | (1 << 7); //int2cfg

       LOC_INT_CTRL_IDX &= 0xff00; //icidx

       //clear vector field
     LOC_INT_CTR_VALUE &= 0xffffff00;

   //set vector field

  LOC_INT_CTR_VALUE |= (1 << 27)\

                                         | (nInfo);

//trigger soft interrupt
LOC_GENARATE_SOFT_INT_VALUE &= 0xff00; //ivector

}

nInfo: Correspond to  interrupt status register .

Thanks!

Hi,

I couldn't get a chance to look through your code detail. I'm very busy with our silicon production related job these days. Instead, I attached my hyperlink test project for your information. you can get some idea how to setup interrupt from my Hyperlink_SW_Interrupt_test.c and I confirmed this on a board which has two DSPs.

Use this code for your reference. I'm not sure how you could run both program at the same time, but your procedure might be bad. please try the mechanism I used in the example code also for your implementation.

  3326.Hyperlink_EVM_example_LE.zip

Albert

hello,si cheng:

         I am working with C6678 hyperlink too,my project is very urgency, but  I don't know how to generate a interrupter with lookback or remote mode after transmited data,I follow your procedure ,but didn't successful, would you provide a successful demo to me for reference,my email is :xiaogeng04@126.com

         Thank's very much!!!