Input video discrete syncs

Hi,

As such, it works any standard timing diagram, so exactly what you are looking for?

Regards,

Brijesh Jadav

What is the expected polarity of DE, HSYNC, VSYNC and FLD?

Is HSYNC expected to be asserted/negated when the data bus does not contain active video?

Is VSYNC  expected to be asserted/negated throughout vertical blanking or can it just be a pulse?

If DE is used can HSYNC just be a pulse?

Can DE be asserted all the time (i.e. not used) if HSYNC is asserted when there is no active video?

Are there any registers in the 8148 memory map that control how the syncs are used? I can't find any registers relating to the VIP module in the TRM (sprugz8a).

Is there a way of writing a capture driver for OMX?

If not, is there a way of using V4L2 capture with OMX H.264 encode?

Hi,

I am not sure about the OMX but, you can surely use V4L2 to capture in discrete sync format, Just couple of change are required as explained in the document. Let me know if you face any issue.

Regards,

Brijesh

So do embedded syncs work in OMX?

Also, can a parallel YUV (ie 24bit) input use embedded syncs? If so which bits should the sync data be presented on?

Hi,

24-bit embedded syncs can also be possible. What exactly you want to do and to which decoder you want to interface HDVPSS capture with. You can go through the appnote and most of the things will be cleared.

V4L2 capture for H.264 encode is shown as a part of GST demos for DM81xx devices. So its very well possible to have V4L2 capture + H.264.