• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 173 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Doubt about GPIO interrupt trigger

Johannes
Mastermind 6240 points

Hi,

I was reading the GPIO guide and in section1.3 about interrupts we have:

"RIS_TRIG and FAL_TRIG are not directly accessible or visible to the CPU. These registers are accessed indirectly through four registers: SET_RIS_TRIG, CLR_RIS_TRIG, SET_FAL_TRIG, and CLR_FAL_TRIG. Writing 1 to a bit on the SET_RIS_TRIG register sets the corresponding bit on the RIS_TRIG register. Writing 1 to a bit of  CLR_RIS_TRIG register clears the corresponding bit on the RIS_TRIG register."

So I'm asking my self why do we have SET_RIS_TRIG and CLR_RIS_TRIG, wouldn't it be easier to set if we have only one register and write 1 or 0 to it?

And if I write 1 to both SET_RIS_TRIG and CLR_RIS_TRIG, what will happen?

Thanks

  • 0
    TI__Mastermind 30825 points

    I'm not sure exactly were the doubt is.

    Implementing it this way allows one to go through and set/clr specific triggers w/o concern for how other GPIO's are configured.  Otherwise with a single register implementation you would need to read a register OR the value and write it back to not end up accidentally clearing other GPIO triggers.  This control is easier for customers to perform in SW.

    As for writing both at the same time, it's indeterminate.  That said, it's not logical to write code which would write both of them at the same time.

    Best Regards,

    Chad