Hello,
We experience low memory bandwith when executing our streaming algorithm with input data on L2SRAM, caused by cache miss stalls.
Reading the "C66 cache user's guide" I learned about miss pipelining, which allows fetching two cache-lines in one stall.
The document mentions a touch()-function which performs memory access in a way to allow for miss pipelining, however I weren't able to find which library contains it.
Any hint is very welcome =)
Thx