I am trying to use the McASP in the AM1806 and I am having problems. I have set up the McASP using the software in the mcasp example in the AM1808 StarterWare. The McASP is set up in the I2S format with word size set for 16 bits and the slot size set for 16 bits. The frame has two slots. The FS and CLK signals are external and meet the voltage specifications and are clean and stable.
The problem comes when I try to send 0xFF55 in slot 0 and 0x0 in slot 1. When I observe the data on the I2S bus I noticed that in one frame the data is correct but in the next frame the data in slot 0 is not 0xFF55 but 0xFEAB. The transmit data is always high during the length of slot 1. Basically the data has been shifted one bit to the left. This pattern then repeats with every alternate frame having the data shifted by one bit (i.e. 0xff55 is sent as 0xFEAB).
The only thing that is different about this I2S setup from a "standard" setup, is that my FS signal is only high for one clock transistion. Normally you would expect the FS signal to be low for 16 clock cycles (data bits in slot 0) and then high for 16 clock cycles (data bits in slot 1). But the equipment that I'm interfacing to has the FS signal low for 16 clock cycles and then FS is high for only one clock cycle.
I have verified that I am sampling on the correct edge of the clock and that the clk signal is clean. Since the bits are shiffted in alternate frames I suspect either a setup issue or a issue with the McASP.
Can the McASP support this type of I2S configuration? Is there a way to specify that the slot size for slot 0 that is different from slot 1? What could be cusing the McASP to shif the data out incorrectly? It looks like on the alternate frames the McASP thinks the word size is 15 and not 16, could that be causing the data to be shifted to the left?
