configuring cache in linker cmd file

Liz

Hi,

In an application based on a StarterWare example, I have

MEMORY {
CACHE_L2 : origin = 0x11810000, len = 0x30000
CACHE_L1P : origin = 0x11e00000, len = 0x8000
CACHE_L1D : origin = 0x11f00000, len = 0x8000
L2RAM : origin = 0x11800000, len = 0x10000
}

in the linker.cmd file. Does this give the linker and processor enough information that I want to use CACHE_xx as cache? Do I have to configure some registers? I understand that only certain configurations are allowed, for example in L2, you could have 128K as RAM and 128k as cache. But the linker.cmd makes me think I can split L2 in any way I want.

Thanks

over 12 years ago

0 Radhesh Bhat over 12 years ago

Genius 4590 points

Hi Liz,

Linked cmd file only gives information about the memory map, it does not tell compiler about hoe much cache or RAM to reserve. Only way to do this is by configuration registers available for both L1 and L2.

0 Liz over 12 years ago in reply to Radhesh Bhat

Intellectual 440 points

if I only use half of the L2 as cache, does the cache exists on the lower half (starts 11800000) or the higher half (starts 11820000)?

It seemed every time I tried to enable half of the L2RAM, my program crashes mysteriously. Please have a look if I am doing it right.

in the cmd file:

MEMORY {
   CACHE_L2    : origin = 0x11820000,  len = 0x20000
   CACHE_L1P   : origin = 0x11e00000,  len = 0x8000
   CACHE_L1D   : origin = 0x11f00000,  len = 0x8000
   DDR2        : origin = 0xc3e00000,  len = 0x100000
   L2RAM       : origin = 0x11800000,  len = 0x20000
   L3_CBA_BOOT : origin = 0x80000000,  len = 0x80
   L3_CBA_RAM  : origin = 0x80000080,  len = 0x1EF00
   L3_CBA_LINK : origin = 0x8001F000,  len = 0x1000
}

In the C file, app crash if like this, works but slow when I removed the highlighted part.

#define DDR2_ADDR (void *)0xc3e00000
#define DDR2_SIZE (unsigned int)0x100000

{
    /* setup MAR bits to enable cache for DDR2 */
    CacheEnableMAR((unsigned int)DDR2_ADDR, DDR2_SIZE);
    /* Enable Cache */
    CacheEnable(L1PCFG_L1PMODE_32K | L1DCFG_L1DMODE_32K | L2CFG_L2MODE_128K);
}