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L3 Interconnect

Fabrizio D'Amato1
Prodigy 80 points

HI All,

I've been working on the OMAP4 processor. Actually I'm quite interested to get better the performance for the NAND flashes and Ram accesses. On the TRM I read that almost every peripheral has been connected by the L3 NoC interconnect bus, and as far as I got that is able to guarantee the QoS on the channel regulating the bandwith at runtime. So my concern is to figure out how to program it in ordert to get the best in matter of performance for my personal purpose, because I'm pretty sure that by default the L3 has set for generlal purpose stuff.

So I'll be glad to have some application note or every documents you can give me about the L3 bus.

Thanks in advance,

Fabrizio

 

  • 0
    Guru 31670 points

    Fabrizio,

    What is the current NAND performance that you are getting? What is your target?

    I guess the ch-13 Interconnect is sufficient for tuning L3 depending on your use case. Also you can modify the L3 clocks. 

  • 0 in reply to Renjith Thomas
    Prodigy 80 points

    Hi,

    First of all, thanks to have answered me. Currenty the performance I've been getting for a while are stuck at about 15 MB/s. I guess It would be possible to achieve something by far better. I know that increasing the clock frequency I will get all the system faster but my purpose is going to reach something any better once I double the clock.

    Using the Logic Analyzer I figured out that the bottle neck of the overall system is the time to copy the data from the buffer prefetch to the Ram. So the first step I made It was to enable the data cache. That has helped me a lot, but I've been stuck at this point so far. I read from the datasheet that It should be possible to tune the L3 interconnect bus for a specific purpose but I'm still guessing how to do it.

    Thanks a lot for the support,

    Fabrizio

     

     

  • 0 in reply to Fabrizio D'Amato1
    Guru 31670 points

    Fabrizio,

    I believe you are getting a good throughput. This can be improved even further to 20MB/s range, I believe. 

    How are you reading the data from NAND to RAM? Are you using DMA or ARM to read? If you are using ARM, can you check the NAND read buf code? You can optimize this by loop unrolling or writing inline assembly code.