Dear support,
I am referencing the following information found on the E2E where Chad provided a very good answer. http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/189169/678701.aspx#678701
I have a very similar question on another infrastructure. Chad refers to example in the C6678 PDK library. Can this example be used on the C6670. I am asking because there is no available example in c:\ti\pdk_C6670_1_1_0_3\packages\ti\csl\example.
It seems that on the C6670, there is not one CIC per core. It seems that one CIC (CIC0) reduces the number of secondary events down to 18 for each core. These events are added to the primary events and can be mapped individually or combined to generate a physical interupt to the CPU.
CIC1 and CiC2 are used to generate events o other peripherals like the EDMA. Do you also have examples using the EDMA inside the SDK?
Aymeric