Hi,
I'm working on a project where 16-bit Rx samples at 750Ks/s are received on McBsp0 of a C6418, coming from Ads8363 (4 channel) or, during startup test loop, coming from McBsp0 tx via digital loopback.
In both cases rx samples are organized as 4x16-bit element frames, and, to save cpu, they must be stored in ram directly by Edma, without additional CPU effort to process channel indication bits associated to samples, and related data reformat and store.
The Edma channel for McBsp rx is configured as 1-dimensional transfer, event triggered, each parameter set being structured as 4096 4-elements frames.
The problem is how to sync tx and rx sample flow in a way that the slots for the 4 channels are stored in right memory positions by Edma.
To get this two point must be satisfed:
1) I must know or set the time on which any start frame element is coming to McBsp DRR. This is not my real problem now. In the McBsp digital loopback case there is a deterministic phase shift between sample entering DXR on tx and sample entering DDR on rx, that can be experimentally checked (I use common internal clock and frame sync generation on both tx and rx). In case of Ads8363, instead, I can set this time via M1/M0 signals (see thread ).
2) At the time a start frame element is to come to McBsp DDR, I have to start the related Edma channel so that this element will be processed as the first of the start Edma parameter set.
Surprisingly to me point 2) is being a bad problem (or, more probably I do something wrong), at least for the loopback case I am trying to set up.
I describe the procedure that I use in case of McBsp digital loopback.
- Edma is pre-configured for EDMA_CHA_XEVT0 and EDMA_CHA_REVT0, both event disabled. Parameter ram and transfer completion interrupts (8 tx and 9 rx) are correctly configured (previously tested).
- I start McBsp0 in digital loopback. Also in this case I have previously tested that the overall loopback is working.
- During the remaining very short procedure HWI are disabled to avoid interferences.
- I poll for XRDY high and immediately write on DXR, causing XRDY to go low.
- I again poll for XRDY high and immediately write on DXR. Immediately after I enable Edma XEVT0 and REVT0. Now I have almost 1 sample time (1.3us) for DXR to go high, and for both Edma channel to activate and get the next tx and rx sample as the starting one.
Now I expect that tx and rx are in a given phase. Not necessarily the one I need, but the same phase every time I restart the system (which is a 6418EVM).
In other words, enabling XEVT0 and REVT0 at (almost) the same time, at the beginning of a tx transfer, I expect to receive, let me say, channel 3 where I'd need channel 1, but, every time I restart the system, I always get channel 3 in that position. Once obtained this, the rest is only a delay tuning.
Completely false. Every time I restart the board the delay is different. One time I have channel 3 on 1, one time channel 2 on 1 and so on. And I don't see any statistic that could reveal a critical timing (es. channel 3 most of times, and channel 2 or 4 some times).
I also thought that syncing to the beginning of a tx transfer could be the best time to enable Edma tx but could be critical for Edma rx (I don't know the exact phase of tx and rx transfers) and I also tried to invert the Edma enable sequence (first rx then tx) or to delay Edma rx enable (less than a sample time of course).
There is a timing problem in edma channels activation that I'm not able to handle or understand. But this should be feasible otherwise I'll never be able to make such a loop or use ADS8363 witout the channel indication bits.
Any hint about this is very appreciated. I am currently in a critical phase (people working on signal processing isr expect all this to work for tests and product).
Thanks
Alberto
