Two core access same address in MSMC

Zhao Shui

Other Parts Discussed in Thread: SYSBIOS

Hi,everyone

I want to let two cores share the same data in MSMC,and that is what I've done:

Firstly,creat an int variable "flag" in project1 and then got the 1.out. In the .map file, "flag" is placed in address 0x0c0028b8

Secondly,in project2,creat an int pointer "check" and initialize the check to make it point to 0x0c0028b8,in which case I assume the (*check) means exactly the value of "flag",and then got the 2.out.

But when I debug by loading 1.out to core0 and 2.out to core1,it seems 2.out can't find the value stored in 0xc0028b8.

In the debug session,when I choose core0,the memory browzer shows at address 0x0c0028b8 the "flag" is set 1 as I wish.When I change to core1,the memory browzer shows at address 0xc0028b8 is 0.

some more detarils:

I use custom platform file for project1 and 2.

For project1 all data in MSMCTX(o=0x0c000000,l=0x00200000),For project 2 all data in MSMCRX(o=0x0c200000,l=0x00200000),in another word I divide the MSMC into two parts.

Is that why core 1 don't konw what is happening in core0's zone?But I assume the MSMC is known to all cores all the time.

Could anyone please point out where my problem lies?Thank you very much.

Zhao.

over 13 years ago

0 Yokoyama, Atsushi over 13 years ago

TI__Expert 7180 points

Hi Zhao,

Unfortunately, C66x multicore DSP doesn't guarantee coherency between L1D and MSMC SRAM (in shared L2 mode). Please refer "Cache coherency control" on the page 5 of SPRY150A (http://www.ti.com/lit/wp/spry150a/spry150a.pdf).

We need manual cache write-back and invalidation and also MFENCE to share variables on shared L2 memory among cores. (SYS/BIOS cache operation library automatically issues MFENCE instruction.)

Best Regards,
Atsushi

0 Zhao Shui over 13 years ago in reply to Yokoyama, Atsushi

Intellectual 910 points

Hi, Atsushi

It's nice to see you again and thank you for your advice.

I'm wondering even if I've already put all my data in MSMC,do I still have to keep the coherency between L1D and MSMC SRAM for other cores to get the data in MSMC?

So what I should do is to move MSMC data to the core's L1D before it can be accessed by the core,Do I understand it right?

Best Regards,

Zhao

0 Yokoyama, Atsushi over 13 years ago in reply to Zhao Shui

TI__Expert 7180 points

Hi Zhao,

You're welcome!

> I'm wondering even if I've already put all my data in MSMC,do I still have to keep the coherency between L1D and MSMC SRAM for other cores to get the data in MSMC?

Yes, you are correct.

There are roughly two types of solutions. One is, completely disabling cache on MSMC by accessing SL3 mode described on the SPRY150A. Another is, manual cache operations between reader and writer cores.

A very simple example of manual cache operations are as following:

#include <ti/sysbios/family/c66/Cache.h>

void func(void)
{
    Cache_wbInv((Ptr) 0x0c0028b8, 4, Cache_Type_ALL, TRUE);
    (*(int*) 0x0c0028b8) ++;
    Cache_wbInv((Ptr) 0x0c0028b8, 4, Cache_Type_ALL, TRUE);

    // ...
}

In the BIOS .cfg file, we need to declare

var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');

Regards,
Atsushi

0 Zhao Shui over 13 years ago in reply to Yokoyama, Atsushi

Intellectual 910 points

Hi,Atsushi

It seems I still got a lot to read and learn before I can handle my problem by myself.

Thank you for your patience and since you've already given me enough advice,I believe I can handle it at last.：)

Best Regards,

Zhao

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Two core access same address in MSMC