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6657 Spi workaround

will Resnick
Expert 2155 points

Hi,

  I found a spi workaround to access CS0 from the 80 pin header from this e2e thread:  http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/212050/752026.aspx

Will this workaround cause my NAND boot to now not work.  I realize the NOR boot is now not possible.

Thanks,

Will

  • 0
    TI__Mastermind 46460 points

    Will,

    The EVM modification described in the other thread allows use of the SPI port over the 80-pin expansion connector.  This modification disables the on-board SPI NOR FLASH device.  This has no impact on the on-board NAND FLASH device attached to the Async EMIF-16 bus.

    Tom