Choosing adequate gigabit PHY for DM8168

Ok, it seems that EMAC requires clock on EMAC_TXCLK only on initialization. As a workaround, we enabled EMAC (because we can only write to Lantiq PHY via EMAC MDIO), then disabled auto-negotiation and forced 100 Mbit/s full duplex GMII copper mode so the PHY starts outputting the clock on EMAC_TXCLK, and then restarting the EMAC so it can get reinitialized while the clock is running. After that, auto-negotiation gets enabled by the generic driver and ethernet works fine both in U-Boot and Linux in all modes, thus it's solvable in software.

This issue should be described more clearly in Sitara/Integra/DaVinci silicon errata, it's pretty cryptic now.

Hi Ivan,

Could you post the code changes you made to implement the workaround?  We are having the same problem with our custom board which uses a Micrel KSZ9021GN PHY.

Did you have to modify U-Boot soruce and the kernel source or just U-boot?

Thanks,

Paul Randall

Hi Paul,

Below are the official guidelines when you add a custom ethernet PHY:

http://processors.wiki.ti.com/index.php/TI81xx_PSP_Porting_Guide#Ethernet_Driver_-_Adding_Custom_Ethernet_Phy

Regards,

Pavel

Hi Paul,

Here are our changes to davinci_emac.c, ethernet works OK now (it's Lantiq 1 Gbit PHY, but registers should be similar). We introduced changes only in U-Boot. Linux driver works OK.

5444.davinci_emac.diff.gz

Hi Ivan,

Thanks for posting your changes to davinci_emac.c.  I tried making similar changes to our U-boot but I am still having problems.  I can get U-boot to boot, but it only negotiates to 100 Mbit full duplex, not 1 Gbit.  U-boot is then able to download the kernel via TFTP, but when the kernel starts, the link light goes out on our switch and the kernel gets stuck trying to acquire an IP address via DHCP.

I had a couple of questions about your changes.

(1) In U-boot, the gen_auto_negotiate() function has the following code:

#ifdef DAVINCI_EMAC_GIG_ENABLE
    davinci_eth_phy_read(phy_addr, PHY_1000BTCR, &val);    /* Read from GCTRL */
    val &= ~PHY_1000BTCR_1000FD;    /* Disable 1000BASE-T full-duplex advertising */
    val &= ~PHY_1000BTCR_1000HD;    /* Disable 1000BASE-T half-duplex advertising, since TI8168 does not support it */
    val &= ~(1 << 10);        /* Advertise PHY as single-port device */
    val &= ~(1 << 12);        /* Disable master/slave manual configuration value */
    davinci_eth_phy_write(phy_addr, PHY_1000BTCR, val);    /* Write to GCTRL */
    davinci_eth_phy_read(phy_addr, PHY_1000BTCR, &val);
    debug_emac("gen_auto_negotiate() GCTRL before auto-negotiation: 0x%X\n", val);
#endif

It looks like the code is disabling Gigabit autonegotiation advertisement by clearing PHY_1000BTCR_1000FD and I didn't see it re-enabled anywhere else.  I assume this is why U-boot only autonegotiates to 100 Mbit.  I tried commenting out the line that clears PHY_1000BTCR_1000FD, but then I wouldn't get a link at all in U-boot.  Do you get a 1 Gbit connection when U-boot boots?

(2) In davinci_emac_initialize(), there was some code that set some registers specific to the Lantiq PHY11G (PHY_MIICTRL_REGISTER and PHY_PHYCTL2_REGISTER).  I don't have similar registers in the Micrel KSZ9021GN PHY that I am using.  Was it necessary to make these changes for the workaround, or were these changes made for other reasons?

Thanks,

Paul

Hi Paul,

1) Indeed our U-Boot works in 100 Mbit mode, because our primary concern was to have 1 Gbit mode working in Linux (for rootfs on NFS server, various file transfer needs etc). For U-Boot, connection is needed only to fetch kernel image so 100 Mbit is OK.

Originally, there were two problems in U-Boot:

1. Lantiq PHY is set to fiber mode by default register values, so we first set the appropriate mode for PHY and disable autonegotiation, and then reset the EMAC.
2. When connected to a gigabit switch, there was no way to establish connection because of the missing TXCLK, so we disabled gigabit advertising and "capped" connection to 100 Mbit max (to make sure the clock is present when Linux takes control).

So when Linux takes over and resets the EMAC again, it negotiates gigabit mode fine (because there was TXCLK present) and the connection works OK. So for U-Boot, maybe you can try to:

1. Set the PHY, disable 1Gbit advertising and disable autonegotiation
2. Reset EMAC
3. Establish 100 Mbit connection via autonegotiation
4. Add 1Gbit advertising to PHY
5. Reset EMAC again
6. Since EMAC had the TXCLK before last reset, maybe it will now work in 1Gbit mode using a/n

Our U-Boot driver obviosly has room for improvement but it's working OK here as it is, compared to original state.

2) They were made with other reasons because Lantiq supports both copper and fiber, as well as multiple MII modes - RMII, GMII, test etc. MIICTRL_REGISTER is "Media-Independent Interface Control" register and PHYCTL2_REGISTER is "Physical Layer Control 2", both are PHY-specific. PHYCTL2 settings are not essential, I added them just in case (descriptions are in comments). MIICTRL is used to set appropriate mode, so if Micrel supports only GMII/MII copper, you can skip all this stuff.

Fire Lord said:

i download the document of "5444.davinci_emac.diff.gz", but i do not know how to uncompress it. can you tell me?

If using Ubuntu Linux OS:

$ gunzip  5444.davinci_emac.diff.gz


BR
Pavel

Pavel

      Thank you for reply.

      I have got the file 5444.davinci_emac.diff, but i am using KSZ9021GN, it doesn't work. Do you have the other files tht can make the KSZ9021 work?

Fire Lord said:

Do you have the other files tht can make the KSZ9021 work?

No I do not have files.

See if the below e2e threads will be in help:

Regards,
Pavel

Hi Paul,

I am working on custom DM8168 board and have VSC8502 dual PHY, i got  phy_id 0x18 and also applied your patch for 1 GIG but not able to ping,

By using the mii command getting the dump value as :

TataPower8168_EVM#mii device
MII devices: 'GENERIC @ 0x18'
Current device: 'GENERIC @ 0x18'
TataPower8168_EVM#mii dump 0x18 0-5
0.     (1040)                 -- PHY control register --
  (8000:0000) 0.15    =     0    reset
  (4000:0000) 0.14    =     0    loopback
  (2040:0040) 0. 6,13 =   b10    speed selection = 1000 Mbps
  (1000:1000) 0.12    =     1    A/N enable
  (0800:0000) 0.11    =     0    power-down
  (0400:0000) 0.10    =     0    isolate
  (0200:0000) 0. 9    =     0    restart A/N
  (0100:0000) 0. 8    =     0    duplex = half
  (0080:0000) 0. 7    =     0    collision test enable
  (003f:0000) 0. 5- 0 =     0    (reserved)

1.     (796d)                 -- PHY status register --
  (8000:0000) 1.15    =     0    100BASE-T4 able
  (4000:4000) 1.14    =     1    100BASE-X  full duplex able
  (2000:2000) 1.13    =     1    100BASE-X  half duplex able
  (1000:1000) 1.12    =     1    10 Mbps    full duplex able
  (0800:0800) 1.11    =     1    10 Mbps    half duplex able
  (0400:0000) 1.10    =     0    100BASE-T2 full duplex able
  (0200:0000) 1. 9    =     0    100BASE-T2 half duplex able
  (0100:0100) 1. 8    =     1    extended status
  (0080:0000) 1. 7    =     0    (reserved)
  (0040:0040) 1. 6    =     1    MF preamble suppression
  (0020:0020) 1. 5    =     1    A/N complete
  (0010:0000) 1. 4    =     0    remote fault
  (0008:0008) 1. 3    =     1    A/N able
  (0004:0004) 1. 2    =     1    link status
  (0002:0000) 1. 1    =     0    jabber detect
  (0001:0001) 1. 0    =     1    extended capabilities

2.     (0007)                 -- PHY ID 1 register --
  (ffff:0007) 2.15- 0 =     7    OUI portion

3.     (0631)                 -- PHY ID 2 register --
  (fc00:0400) 3.15-10 =     1    OUI portion
  (03f0:0230) 3. 9- 4 =    35    manufacturer part number
  (000f:0001) 3. 3- 0 =     1    manufacturer rev. number

4.     (01e1)                 -- Autonegotiation advertisement register --
  (8000:0000) 4.15    =     0    next page able
  (4000:0000) 4.14    =     0    reserved
  (2000:0000) 4.13    =     0    remote fault
  (1000:0000) 4.12    =     0    reserved
  (0800:0000) 4.11    =     0    asymmetric pause
  (0400:0000) 4.10    =     0    pause enable
  (0200:0000) 4. 9    =     0    100BASE-T4 able
  (0100:0100) 4. 8    =     1    100BASE-TX full duplex able
  (0080:0080) 4. 7    =     1    100BASE-TX able
  (0040:0040) 4. 6    =     1    10BASE-T   full duplex able
  (0020:0020) 4. 5    =     1    10BASE-T   able
  (001f:0001) 4. 4- 0 =     1    selector = IEEE 802.3

5.     (cde1)                 -- Autonegotiation partner abilities register --
  (8000:8000) 5.15    =     1    next page able
  (4000:4000) 5.14    =     1    acknowledge
  (2000:0000) 5.13    =     0    remote fault
  (1000:0000) 5.12    =     0    (reserved)
  (0800:0800) 5.11    =     1    asymmetric pause able
  (0400:0400) 5.10    =     1    pause able
  (0200:0000) 5. 9    =     0    100BASE-T4 able
  (0100:0100) 5. 8    =     1    100BASE-X full duplex able
  (0080:0080) 5. 7    =     1    100BASE-TX able
  (0040:0040) 5. 6    =     1    10BASE-T full duplex able
  (0020:0020) 5. 5    =     1    10BASE-T able
  (001f:0001) 5. 4- 0 =     1    selector = IEEE 802.3

My PHY link is up (LINK = 1000000) on u-boot, Fails to ping,

Any configuration need to write for VSC8502 Dual PHY, Please help me resolve the issue.

Also find the our design in the attachment.

Thanks,

Vidya