Using this:
http://processors.wiki.ti.com/index.php/DM36x_to_DM368_NAND_UBL_porting_guide
as a reference, I'm updating my UBL to use the DDR timings of the DDR2 module we are using in our design. I'm going through all of the registers, but found that bit 27 is enabled on SDBCR in both the UBL sources and the link above. According to the documentation, this must always be 0. What is this bit, and is this a mistake in the UBL sources?