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EDMA Interrupt Handling using Resource Manager

SM85
Prodigy 150 points


Hardware: c64x+

I'm using resource manager for edma3 transfers

1. While polling on Global IPR register, edma transfers are complete & it takes 2,000 cycles for 1 block transfer. Works fine

2. When I use ISR along with completion handler callback, it takes 200 cycles for same block & transfer is incomplete. When I wait for 1000 cycles after a dma transfer I find dma transferred data fine.

What I see in the ISR shadow registers are used, am I missing any settings for this? I'm using region ID = 1

  • 0
    Genius 4590 points

    Hi ,

    What is the bit value you have set for EDMA3_DRV_OPT_FIELD_TCCMODE in the OPT field (11th bit)? The interpretation of the field is

    TCCMODE Transfer complete code mode. Indicates the point at which a transfer is considered completed for
    chaining and interrupt generation.
    0 --- >Normal completion: A transfer is considered completed after the data has been transferred.
    1 ----> Early completion: A transfer is considered completed after the EDMA3CC submits a TR to the
                 EDMA3TC. TC may still be transferring data when the interrupt/chain is triggered.

  • 0 in reply to Radhesh Bhat
    Prodigy 150 points

    Hi Radhesh,

    Thanks for your reply.

    OPT value is 0x00900004 i.e

    Bit 2 SYNCDIM 1 AB-synchronized

    Bit 20 TCINTEN 1Transfer complete interrupt is enabled

    Bit 23 ITCCHEN 1 Intermediate transfer complete chaining is enabled

    Bit 11 TCCMODE is RESET 0

    -SM

  • 0 in reply to SM85
    Genius 4590 points

    SM85 said:
    Bit 23 ITCCHEN 1 Intermediate transfer complete chaining is enabled

    Any specific reason you have enabled this bit?

  • 0 in reply to Radhesh Bhat
    Prodigy 150 points

    For AB Synchronized & C Count = 1 we will get 1 TR completion interrupt.

    With TCCHEN = 0, ITCCHEN = 1 does the above hold true?

    Thanks,

    Surjashis

  • 0 in reply to SM85
    TI__Guru* 84110 points

    Surjashis,

    With ABSync and CCNT=1, ITCCHEN is not used. The fact that you set it to 1 confuses the discussion, as is the case when extra or redundant bits are set.

    If the only thing you changed from the polling case to the interrupt case is the use of the IPR bit (no other changes in the PARAM or other EDMA3 registers, other than possibly EDMA3->IER), then your situation does not make sense. Something else must be happening.

    The timing difference may be explained by a number of factors like inefficient polling code, but not the fact that you got the interrupt before the transfer was complete.

    Where are you transferring data from and to? How much data are you transferring?

    What other conditions affect the transfer?

    Regards,
    RandyP