A few questions on DM3730 GPMC:
(1) How to configure the GPMC timing options for addr/data multiplexed synchronous mode (with bursts) for a non-Flash device that has > 2k addresses, and also a clarification on how the write enable signal works in both single-access and burst modes when the GPMC is configured for address/data multiplexed transfers.
(2) Clarification on some information in User Guide: The user guide has 2 different pictures of a burst-write transfer: Fig 10-20 describes address/data multiplexed mode without actually stating that it is addr/data multiplexed mode, Fig 10-21 explicitly states that this is addr/data multiplexed mode. The 2 pictures are different in how the nWE signal behaves.
(3) the xxOFFTIME and xxCYCLETIME settings are described differently Vs how they are shown on the waveforms.
(4) Can GPMC clock be forced to stay active for 1-2 cycles after the write transfer is complete?
regards
