I am implementing an EDMA transfer from the GPMC to the DDR3 to transfer exactly 161 16-bit words at a time. In watching the chip select on the GPMC I found that if I have the number of words set to 161 I get 168 pulses on the CS. If I change my code to 160 words then I get 160 pulses on the CS. So it appears that the GPMC accesses are in increments of 8 (I tried 162 words as well and got 168 pulses).
Is this increment of 8 GPMC accesses configurable anywhere? Ideally I need 161 accesses for 161 words.
Thanks in advance.
