Other Parts Discussed in Thread: SYSBIOS
we are trying to use C6657 EVM to receive PCIe MSI interrupts (c6657 is configured as EP). I tried to write 0/8/16 to MSI_IRQ to trigger MSI to core 0 and test the MSI reception. But the isr is not triggered reliably. Most of the time, it is not hit (I had a global counter and also break point in isr). Occationally, it works. Once that happened, the hwi can always trigger the isr.
I am using sysBios 6.33.6.50, PDK for C6657 1.1.1.4, MCSDK 2.1.1.4 and CCS 5.2.1.00018
I suspect that I missed some initialization somewhere. I checked the following:
1. MSI_EN is set to be 1, LEGACY_[A|B|C|D]_IRQ_ENABLE_SET are all 0
2. in my cfg file, I have the following
var hwi0Params = new Hwi.Params();
hwi0Params.instance.name = "pcie_msi_core0";
hwi0Params.eventId = 17;
Program.global.pcie_msi_core0 = Hwi.create(5, "&pcie_msi_isr", hwi0Params);
3. after I wrote to MSI_IRQ, I noticed that MSI0_IRQ_STATUS_RAW is updated based on the value I wrote to MSI_IRQ.
4. How can I debug the interrupt chain, making sure that the MSI irq is sent to chip INTC and chip INTC generates HWI and HWI triggers isr? Any registers I can check?
Weichun
