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C6457 L2 ECC capability.

Hector Rivera
Intellectual 2025 points

 

It is my understanding and the understanding of one of my customers that the C6457 has L2 ECC.  They can[not] find information on it.  Can some one let me know details on the ECC for C6457.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/439/p/11420/44408.aspx#44408

Regards,

Hector Rivera

  • 0
    TI__Intellectual 2025 points

    Sorry,

    I have a typo in the previous e-mail.  The cusotmer cannot find the ECC inforamtion.  Can someone tell me where the ECC capability for the C6457 shown?  I looked at the mega module user guide and I did not find any reference to the ECC capability.

     

    Regards,

    Hector Rivera

     

  • 0 in reply to Hector Rivera
    TI__Guru* 84110 points

    Hector,

    ECC is generally not documented for our internal memories. This is used to keep the high reliability of our internal memories as the transistor sizes keep shrinking, since the shrink makes them more susceptible to upset events. The addition of ECC logic increases the size of the memory array but also improves the reliability to the very high thresholds that TI requires for its devices; we do not publish that threshold, either.

    We do not offer control over this internal ECC logic and we do not document the design of these internal features. They are mentioned so you can have confidence in the device reliability, but you can otherwise ignore its existence and just assume that every time you read a value from L2 it will be the same as what you wrote there.

    If any customer has concerns with error rates, they could improve those by periodically refreshing the L2 memory using a read-write loop. I have not looked at how to do that, but it would probably require turning off the cache or using EDMA or IDMA. This idea has not been passed through the factory design or apps teams, but it makes sense to me, for what that is worth.

    Regards,
    RandyP