Custom PCB, C6748 DSP, running SYSBIOS 6.34.2.18, XDCtools 3.24.3.33.
I created a custom Platform file, and updated my project to use that custom Platform file. When I change the L2 CACHE(in the platform file) from 128kB to 256kB, rebuild, reload, the ROV correctly shows my L2 Cache size is 256kB. I can switch back to 128kB, rebuild, reload, and again the ROV shows 128kB. So, I'm 99% sure that I have everything linked in correctly, and that my changes to the Platform file are really showing up in my project.
When I view the CACHE tab from app.cfg, things are different. I have Cache (ti.sysbios.family.c64p) in my outline, and when I click on that a "C6x/Cache" tab appears. It correctly shows L1P and L1D (they match my Platform file), however the L2 is always at 128K (even when I have the platform file changed to 256k). What gives?
Does the C6x/Cache tab track changes in the platform file?
When I attempt to change the L2 Cache in the C6x/Cache tab, I get warnings about user changed something. Should you change the Cache settings from the C6x/Cache tab?
What is the correct way to change the cache settings: Platform file ..or.. C6x/Cache tab?
Thanks, Dean