We have an application running on TMS3200DM643AZDK (600 MHz). The code resides on SDRAM and so does the data. For a very simple application that involves reading 3 data from an array and writing the result back into the array inside a loop takes 53 nsec on average per iteration. To me that appeard to be a high number considering that 2 of the data read are in sequence and could benefit from cache and burst mode of the SDRAM. The data written back to the array is random access. To investigate the timing I wrote a test program from scratch that would simply write into a large array some integer (32 bit) values. So that I am able to measure the time it takes to write an int into SDRAM I have made L2 cache size to be 0 and ISRAM is 256kB. I initialize the EMIF registers inside the User Init Function that is mentioned in the Global Settings part of the .cdb file of the project. The SDRAM being used is MT48LC4M32B2 (x2 for 64 bit interface) and is meant for speeds higher than 133MHz as required by TI specifications. The connections comply with suggested connections as mentioned in SPRA433E.ECLKIN signal is 133MHz. I have measured the average memory write to be 70ns/integer by measuring the time it takes for a large chunk of data to write by toggling a pin before the writing is started and after the writing is completed. This value matches with the !WE period. However I fail to understand since it is 64 bit interface the !WE signal should have period double of average writing time/integer. One write to the SDRAM is taking 9 clock cycles instead of 3. Since we are writing in sequence it should take even less because by default the EMIF gets into burst mode. My code is given below:
******** FILE InitSDRAM.c ***************
void Init_SDRAM(void) {
// Initilaize SDRAM Registers
// GBLCTL - Use default value
// CE0CTL
*(int *)0x01800008 = 0x000000D0;
// CE1CTL
*(int *)0x01800004 = 0x000000D0;
// CE2CTL
*(int *)0x01800010 = 0x000000D0;
// CE3CTL
*(int *)0x01800014 = 0x000000D0;
// CESEC0A
*(int *)0x01800048 = 0x00000000;
// CESEC1A
*(int *)0x01800044 = 0x00000000;
// CESEC2A
*(int *)0x01800050 = 0x00000000;
// CESEC3A
*(int *)0x01800054 = 0x00000000;
// SDTIM
*(int *)0x0180001C = 0x00000FFF;
// SDEXT
*(int *)0x01800020 = 0x0004052B;
// SDCTL
*(int *)0x01800018 = 0x57227000;
// Set GPO
*(int *)0x01B00000 = 0x000F;
*(int *)0x01B00004 = 0x000F;
}
****************** File: TestMemoryMain.c ***********************************
#define POWER_IS_ON 1
#define SDRAM_ARRAY_SIZE 0x00010000
int SDRAMWriteArray[SDRAM_ARRAY_SIZE];
void main(void)
{
int i, j, k;
int GPO = 0x00;
int toggle = 0;
*(int *)0x01B00008 = GPO;
while (POWER_IS_ON)
{
*(int *)0x01B00008 = (toggle ^= 1) ? 0x000001 : 0x000000;
for (i = 0; i < SDRAM_ARRAY_SIZE; ++i)
{
SDRAMWriteArray[i] = i;
}
}
}
I have made sure that only the array resides in the SDRAM by making .far section in compiler section as SDRAM (ONLY!) in .cdb file. Rest of the sections reside in the iSRAM.
In build options I have optimized for speed and made the Memory models Far Aggregate Data.
Please point out where did I go wrong in the SDRAM settings or other place.
What is expected throughput for SDRAM running at 133MHz?
Regards,
-Ashok Rajpal