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Is it possible to use more than one MSI INT from same end point ?

Koray Korkmazer
Intellectual 820 points

Hello,

Here is the PCIe scenario :

  • DSP(6678) is root complex, and there is a FPGA on the other side as end point. No more nodes on the PCIe network.
  • EP uses MSI to notify RC. Then RC does the data transfer.

Is it possible to enable and use all 8 MSI_INTs by means of the same end point ?
I mean that I want EP be able to send 8 different MSI INTs, so that I can use them to trigger 8 different EDMA transfers. Is it possible ?

As far as I understand from PCIe protocol, I may use just one MSI data for an EP. So that it seems it is not possible to use more than 1 MSI INT for the same EP. But because of this is very critical for my design, I just want to be sure about my analysis.

thanks in advance,
koray.

 

  • 0
    TI__Genius 12065 points

    Koray,

    Please take a look at the "MSI Capability Structure" section in PCI Local Bus Specification Revision 3.0 from PCISIG. Multiple MSI messages could be assigned to the single EP device (supports up to 32 vectors, all 8 MSI_INTs in C66x).

    It should be no limitation for the EP to generate multiple (or all) MSI interrupts to RC. You can enable all the 8 MSI_INT in RC and let EP write different vector values to "MSI_IRQ" register in RC to generate multiple MSI interrupts. 

  • 0 in reply to Steven Ji
    Intellectual 820 points

    Hi Steven,

    I have a question about this issue :
    In the C6678 data sheet, at the end of Table7-38 (System Event Mapping-Primary Interrupt Table), at note 4 it says "CorePac[n] will receive PCIEXpress_MSI_INTn." Does that mean that each core will receive separate MSI INTs ? I understand that MSI_INT0 will be fed to CorePac[0], MSI_INT1 will be fed to Corepac[1], then goes like this for the other cores . Is that right ? Is it not possible to feed all MSI_INTs to the same core (say Core0) ?

    Regards,
    Koray.

     

     

  • 0 in reply to Koray Korkmazer
    TI__Genius 12065 points

    Koray,

    Your understanding is correct that MSI_INT 0-7 will be distributed to Core 0-7 individually.

    There are still 4 vectors in each MSI_INT for single CorePac to use. You may need to add software workaround if you want one CorePac to service the interrupts from other CorePacs (such as IPC, that CorePac_x notify CorePac_y when CorPac_x receives MSI_INT_x).