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C5504, performance degradation

Elina Senkevich
Intellectual 315 points

Hello all,

Can you please advise on if there is a performance degradation in this working method and if so, how can be minimized?

According to SPRUGU6 (sec1.2.1) if SYS_CLK>100 MHz or VDDEMIF=1.8V,  the EM_SDCLK must be equal SYS_CLK/2.

In the design the SYS_CLK=150 MHz and VDDEMIF=1.8V, so EM_SDCLK=75MHz.  Because of this status there are following questions:

  1. How is DSP performance (MIPS) degraded if ALL program memory is placed in external DPRAM and DPRAM is working at half SYS_CLK?
  2. If DSP performance is degraded significantly, what is your recommendation to minimize the degradation?

Thank you.

Regards,
Elina