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cache invalidation for more than 32k L1D

RCReddy
Genius 3575 points

Hi All,

         Probably a novice/basic question..still fine. I have a N descriptors [host descriptors]  and a buffer [each is 64512 bytes] attached to it. Please note both descriptor and buffer are in MSMC-SRAM. I want to modify its contents at some places [say around 1024 bytes scattered at different memory locations within 64512 bytes] in the buffer. I understand if it is continous operation, then i could have opted for EDMA. but since the TO-BE-MODIFIED memory locations are scattered, i can do it manually. In this regard, i plan to do cache invalidation part by part and then write the contents.

what happens if i do cache invalidation of entire 64512 bytes [please note L1D size is 32k only and the memory which i am trying to invalidate is Level2 i.e. MSMCSRAM] ? If i understand there wont be any L2 caching for MSMC-SRAM [unless i do address translation to Level 3 memory]?

Thanks

RC Reddy

  • 0
    TI__Expert 7180 points

    Hi RC,

    As mentioned in the white paper KeyStone memory architecture (http://www.ti.com/lit/wp/spry150a/spry150a.pdf), MSMC RAM is not cached in L2 unless mapping to different address (or SL3 mode in the white paper).  On the other hand, L1D still caches MSMC RAM.

    By the way, if you want to ensure coherency between MSMC RAM (SL2 mode) and EDMA, you may also need cache write-back operation.  The TMS320C66x DSP CorePac User Guide (http://www.ti.com/lit/ug/sprugw0b/sprugw0b.pdf) covers the topics.

    Did the above answer your questions?  If not, could you please explain your questions in detail?

    Best Regards,
    Atsushi

  • 0 in reply to Yokoyama, Atsushi
    Genius 3575 points

    Hi Atsushi,

                    Thanks for reply and at the same time, your answer/reply/response is no way related to my question. I am asking about caching for more > 32k.Let me put it in layman's/detailed/more elaborated language.

    1. I have a buffer.

    2. buffer is of size = 63*1024 byte. = 64512 bytes.

    3. i want to modify randomly scattered locations [around 1024 memory locations] within that 64512 bytes.

    4. I cannot use EDMA.

    5. I want to do step by step caching [say first 8129 bytes invalidation ...modify contents with in them and write back them]. like wise i can do step by step [cache invalidation and writeback for entire 64512 bytes].I am going by this approach

    6. my doubt is what happens if i do cache invalidation of 64512 bytes at once and do alter the contents within those 64152 bytes and do writeback. [please note L1D cache size is 32k bytes]

    Please read my first post and second post again and understand. I read documents, i went through it. I was not able to make out any answer [for the problem/issue i am seeing] from UG's. 

    Thanks

    RC Reddy

  • 0 in reply to RCReddy
    Mastermind 6670 points

    Hi,

    The L1 and L2 invalidation/flush register works on real memory addresses: if they are (whole or a part only) in the cache the operation does something otherwise it does noting.

    So, in general, since you cannot predict what is in cache and what is out (even if the cache is greter or less then your working area), you have to invalidate/flush all the required area.  I think it is simple and less error prone to first invalidate all the area, do your bussines and then flush all. The HW will update only the touched areas.

    You can use L2 registers, even if your memory is not cachable at L2: flush/invalidate L2 automatically flush/invalidate L1.

    To be verified: I see that write only operations don't use the cache. If you never read from the region you need to update, it is enought to first invalidate and then update (write). You must be sure you never read-in any location in the region you are working on.

  • 0 in reply to Alberto Chessa
    Genius 3575 points

    Hi Alberto,

                    Can you stress more on this this "You can use L2 registers, even if your memory is not cachable at L2: flush/invalidate L2 automatically flush/invalidate L1". Are you talking about L2WBAR) and the length (L2WWC) registers. ?

    L2WBAR = &array[0];
    L2WWC = sizeof(array) / sizeof(int);

    Thanks

    RC Reddy

  • 0 in reply to RCReddy
    Mastermind 6670 points

    Yes, L2W* or corresponing CSL routines.